CHAPTER 4 EXTERNAL BUS INTERFACE
4.10.6 2-Cycle Transfer (External -> I/O)
This section explains 2-cycle transfer (external -> I/O) operation.
■ 2-Cycle Transfer (External -> I/O)
Figure 4.10-9 shows the operation timing chart for (TYP3 to TYP0=0000
IOWR=00
Figure 4.10-9 shows a case in which a wait is not set for memory and I/O.
Figure 4.10-9 Timing Chart for 2-Cycle Transfer (External -> I/O)
MCLK
A31 to A00
AS
CSn
RD
CSn
WRn
D31 to D00
DACKn
FR30
compatible
mode
DEOPn
DACKn
Basic
mode
DEOPn
DREQn
•
The bus is accessed in the same way as an interface when the DMAC transfer is not
performed.
•
In basic mode, DACKn/DEOPn is output in both transfer source bus access and transfer
destination bus access.
248
).
H
memory address
idle
I/O address
, AWR=0008
,
B
H