Is Selected - Intel MCS48 User Manual

8355/8355-2
Symbol
ALE
(Input)
AD0-7
(Input)
A8-10
(Input)
CE"i
CE
2
(Input)
IO/M
(Input)
RD
(Input)
IOW
(Input)
Function
When ALE
(Address Latch Enable
is
high,
AD0-7, IO/M,
As-io,
CE, and
CE
enter address
latched.
The
signals
(AD, IO/M,
As-10,
CE, CE) are latched
in at
the
trailing
edge
of
ALE.
Bidirectional
Address/Data
bus.
The
lower
8-bits of
the
ROM
or I/O
address
are applied
to
the bus
lines
when ALE
is
high.
During an
I/O cycle, Port
A
or
B
are
selected based on the latched value
of
ADo.
If
RD
or
IOR
is
low
when
the latched
chip
enables
are
active,
the output
buffers
present data
on
the bus.
These
are the high
order
bits of
the
ROM
address.
They do
not
affect
I/O oper-
ations.
Chip Enable
Inputs:
CEi
is
active
low
and
CE2
is
active
high
.
The
8355 can be
accessed only
when
BOTH
Chip En-
ables are active
at
the time the
ALE
signal latches
them
up.
If
either
Chip
Enable
input
is
not
active,
the
AD0-7
and
READY
outputs
will
be
in
a
high
impedance
state.
If
the latched
IO/M
is
high
when
RD
is
low,
the output data
comes
from an
I/O port.
If
it
is
low
the output data
comes
from the
ROM.
If
the latched
Chip Enables
are active
when
RD
goes
low, the
AD0-7
output
buffers are
enabled and output
either
the selected
ROM
lo
catio n or I/O port.
When
both
RD
and TOR
are
high,
the
AD0-7
output
buffers are
3-state.
If
the latched
Chip Enables
are
active,
a
low on
IOW
causes
the
output
port
pointed
to
by the latched value
of
ADo
to
be
written with the data
on AD0-7.
The
state of
IO/M
is
ignored.
Symbol
CLK
(Input)
READY
(Output)
PA0-7
(Input/
Output)
PB0-7
(Input/
Output)
RESET
(Input)
Tor
(Input)
Vcc
Vss
Function
The
CLK
is
used
to force the
READY
into
its
high
impedance
state after
it
has
been
forced low by
CE
low,
CE
high
and
ALE
high.
Ready
is
a 3-state output controlled
by
CE1, CE2,
ALE
and CLK.
READY
is
forced low
when
the
Chip Enables
are
active
during the time
ALE
is
high,
and
remains low
until
the
rising
edge
of the
next
CLK
(see
Figure
6).
These
are general
purpose
I/O
pins.
Their input/output direction
is
deter-
mined
by the contents
of
Data
Direction
Register (DDR). Port
A
is
selected
for
write
operations
when
the
Chip Enables
are active
and
IOW
is
low
and
a
was
previously latched from ADo.
Rea
d operation
is
selected by either
IOR
low and
active
Chip Enables and
ADo
low,
or
IO/M
high,
RD
low, active
chip enables, and
ADo
low.
This general
purpose
I/O port
is
identical to
Port
A
except
that
it
is
selected
by
a
1
latched
from ADo.
An
input high
on
RESET
causes
all
pins
in
Port
A
and B
to
assume
input
mode.
Wh
en
t
he Chip Enables
are active, a
low
on IOR
will
outpu
t
the selected I/O port
onto the
AD
bus.
IOR low performs
the
same
function as the
co mbin
ation
IO/M
high
and
RD
low.
When
IOR
is
not
used
in
a system,
IOR
should be
tied to
Vcc
("1").
+5
volt
supply.
Ground
Reference.
6-55