Intel MCS48 User Manual page 279

intel
8214
PRIORITY
INTERRUPT
CONTROL
UNIT
i
8
Priority
Levels
ii
Current Status Register
i
Priority
Comparator
Fully
Expandable
High Performance
(50 ns)
24-Pin Dual
In-Line
Package
The
Intel*
8214
Is
an
8-level priority
interrupt control unit (PICU)
designed
to simplify interrupt-driven
microcomputer
systems.
The PICU can
accept 8 requesting
levels;
determine the highest
priority,
compare
this priority to
a software controlled
current status register
and
issue an
interrupt to
the
system along with vector information
to identify the service
routine.
The 8214
Is fully
expandable by
the use
of
open
collector interrupt
output vector information. Control signals are also
provided to simplify this function.
The PICU
is
designed
to
support a
wide
variety of
vectored
interrupt
structures
and reduce package count
in interrupt-
driven
microcomputer
systems.
'Note:
The
specifications for
the 3214
are identical with
those
for
the 8214.
PIN
CONFIGURATION LOGIC
DIAGRAM
£c
SGSQ
INT
Q
clk£
inteQ
GNOC
8214
24
D
v
cc
23
^ici
22
3^
21
3*>
20
3«>
19
3*.
18
3«,
17
3*,
16
3",
15
1]^
14
^
ENLG
13
3
ETLG
PIN
NAMES
INPUTS
REQUEST
LEVELS
IR
;
HIGHEST PRIORITY)
CURRENT STATUS
s3s
STATUS GROUP
SELECT
ECS
ENABLE CURRENT STATUS
INTE
INTERRUPT ENABLE
CLK CLOCK
(INT
FF)
ETB ENABLE LEVEL
READ
ETLG ENABLE THIS LEVEL
GROUP
OUTPUTS
Ao-A,
iST
REQUEST
LEVELS
"1
OPEN
INTERRUPT
(ACT.
LOW) J
COLLECTOR
ENLQ ENABLE NEXT LEVEL GROUP
QT>
ELR
[13>ETLG
(T>
INTE
|T>
5LK
IMTEL CORPORATION ASSUMES NO
RESPONSIBILITY FOR THE USE OF ANY
CIRCUITRY OTHER THAN CIRCUITRY EMBODIED
IN
AN
INTEL
PRODUCT.
NO OTHER
CIRCUIT PATENT LICENSES ARE
IMPLIED
C
INTEL CORPORATION, 1979
7-41