Intel MCS48 User Manual page 416

MODEL
220
FUNCTIONAL
DESCRIPTION
Hardware
Components
The
Intellec Series
II
Model
220
is
a packaged,
highly
integrated
microcomputer development system
consist-
ing of a
CRT
chassis
with a
6-slot
cardcage,
power
sup-
ply,
fans, cables, single floppy diskette
drive,
and two
printed
circuit cards.
A
separate,
full
ASCII keyboard
is
connected
with
a cable.
CPU
Cards
—
The
master
CPU
card contains
its
own
microprocessor, memory,
I/O,
interrupt,
and bus
inter-
face
circuitry,
fashioned from
Intel's
high-technology
LSI components.
Known
as
the integrated processor
board
(IPB),
it
occupies
the
first slot in
the cardcage.
A
second,
slave
CPU
card,
is
responsible
for
all
remaining
I/O control, including the
CRT
and keyboard
interface
and
floppy disk
control. This
card,
mounted
on
the
rear
panel, also contains
its
own
microprocessor,
RAM
and
ROM
memory, and
I/O interface,
thus
in effect
creating a
dual processor environment. Known
as the
I/O
con-
troller (IOC), the slave
CPU
card
communicates
with the
IPB over an
8-bit bidirectional data bus, thus
leaving
the
remaining 5
slots
in
the
cardcage
available
for
system
expansion.
A
block diagram
of
the
IOC
is
shown
in
Figure
1.
System Components
The
heart of the
IPB
is
an
Intel
NMOS
8-bit
microproces-
sor, the 8080A-2, running
at 2.6
MHz. 32K
bytes of
RAM
memory
are
provided
on
the
board using
Intel
16K
RAMs. 4K
of
ROM
is
provided, preprogrammed
with
sys-
tem
bootstrap
"self-test" diagnostics
and
the
Intellec
Series
II
System
Monitor.
The
eight-level
vectored
prior-
ity
interrupt
system
allows
interrupts to be
individually
masked. Using
Intel's versatile
8259
interrupt controller,
the
interrupt
system
may
be user
programmed
to
respond
to individual
needs.
Input/Output
IBP
Serial
Channels
—
The
I/O
subsystem
in
the
Model
220 consists
of
two
parts: the
IOC
card
and two
serial
channels on
the IPB
itself.
Each
serial
channel
is
RS232
compatible and
is
capable
of
running
asynchronously
from
1
10 to
9600 baud
or synchronously from 150
to
56K
baud. Both
may
be connected
to a user defined data
set
or
data
terminal.
One
channel contains
current loop
adapters. Both channels
are
implemented
using
Intel's
8251
USART. They
can be programmatically
selected
to
perform a
variety of
I/O
functions.
Baud
rate selection
is
accomplished
programmatically through an
Intel
8253
interval timer.
The
8253
also serves as a
real-time
clock
for
the
entire system.
I/O activity
through both
serial
channels
is
signaled
to the
system through a
second
8259
interrupt controller, operating
in
a polled
mode,
nested
to
the primary 8259.
IOC
Interface
—
The
remainder
of
system
I/O activity
takes place
in
the IOC.
The IOC
provides interfaces
for
the
CRT,
keyboard,
integral floppy disk and standard
Intellec peripherals, including a
printer,
high
speed
paper tape
reader/punch, and
universal
PROM
program-
mer.
The IOC
contains
its
own
independent
microproc-
essor, also
an
8080A-2. This
CPU
controls
all
I/O
opera-
tions,
as
well
as supervising communications
with the
IPB.
8K
bytes
of
ROM
contain
all I/O
control firmware.
8K
bytes
of
ROM
are
used
for
CRT
screen
refresh
stor-
age and
the floppy disk
buffer.
These do
not
occupy any
space
in
Intellec
Series
II
main
memory
since the
IOC
is
a
totally
independent microcomputer subsystem.
Integral
CRT
Display
—
The
CRT
is
a 12-inch raster
scan-type monitor with a 50/60 Hz
vertical
scan
rate
and
15.5
kHz
horizontal
scan
rate.
Controls
are provided
for
brightness
and
contrast
adjustments.
The
interface to
the
CRT
is
provided through an
Intel
8275
single chip,
programmable
CRT
controller.
The
master processor on
7S
^L
8228
SYSTEM
CONTROLLER
7T
iz
7T
7>
CABLE BUS TO
IPB
7y
82S3
DMA
INTERVAL
TIMER
77
iz
<T
iZ
7V
iZ
77
CONTROLLER
77
Iz
77
\>
Si
77
<Jl
il
77
12.
Figure
1.
I/O
Controller (IOC)
Block Diagram
for
the
Model 220
Intellec Series
II
Microcomputer Development System
9-2