Intel MCS48 User Manual page 212

8755A
8755A
FUNCTIONAL
PIN
DEFINITION
Symbol
ALE
(input)
ADo-7
(input/output)
A8-10
(input)
PROG/CEi
CE
2
(input)
IO/M
(input)
RD
(input)
IOW
(input)
CLK
(input)
Function
When
Address
Latch
Enable goes
high, ADo-7, IO/M,
As-io,
CE2,
and
CE1
enter the address
latches.
The
signals
(AD, IO/M,
As-io,
CE) are
latched
in at
the
trailing
edge
of
ALE.
Bidirectional
Address/Data
bus.
The
lower
8-bits
of
the
PROM
or I/O
address
are applied
to
the
bus
lines
when ALE
is
high.
During an
I/O cycle, Port
A
or
B
are
selected
based on
th
e latched value of
ADo-
If
RD
or
JOR
is
low
when
the
latched
Chip Enables
are
active,
the
output
buffers
present data
on
the
bus.
These
are the high
order
bits of
the
PROM
address.
They do
not
affect
I/O operations.
Chip Enable
Inputs:
CE1
is
active
low
and CE2
is
active high.
The 8755A
can be accessed only
when
BOTH
Chip Enables
are active
at
the time
the
ALE
signal latches
them
up.
If
either
Chip Enable
input
is
not
active,
the
ADo-7 and
READY
outputs
will
be
in
a
high
impedance
state.
CE1
is
also
used as
a
programming
pin.
(See
section
on programming.)
If
the latched
IO/M
is
high
when
RD
is
low,
the output data
comes
from
an
I/O port.
If it
is
low the output data
comes
from
the
PROM.
If
the latched
Chip Enables
are active
when
RD
goes low, the ADo-7 output
buffers are
enabled
and
output
either
the selected
PROM
location or I/O
port.
When
both
RD
and IOR
are high,
the
ADo-7
output buffers are 3-stated.
If
the
latc
hed
C
hip
Enables
are active,
a
low on
IOW
causes the output port
pointed to
by
the latched value of
ADo
to
be
written
with_the data
on
AD0-7.
The
state of
IO/M
is
ignored.
The
CLK
is
used
to
force the
READY
into
its
high
impedance
state after
it
has
been
forced
low by CE1
low,
CE2
high,
and
ALE
high.
Symbol
READY
(output)
PA0-7
(input/output)
PBo-7
(input/output)
RESET
(input)
IOR
(input)
Vcc
Vss
Vdd
Function
READY
isa_3-state
output controlled
by
CE
2
,
CE1,
ALE
and CLK.
READY
is
forced
low
when
the
Chip Enables
are active during the time
ALE
is
high,
and remains low
until
the
rising
edge
of
the next
CLK.
(See Figure
6.)
These
are general purpose
I/O pins.
Their input/output direction
is
deter-
mined by
the contents
of
Data
Direc-
tion
Register
(DDR).
Port
A
is
selected
for write
operations
wh
en
th e
Chip
Enables
are active
and
IOW
is
low
and
a
was
previously latched from
ADo, AD1.
Read
operation
is
selected
by
either
IOR
low
and
active
Chip Enables and
ADo
and
AD1
low, or
IO/M
high,
RD
low, active
Chip
Enables,
and
ADo
and
AD1
low.
This general purpose
I/O port
is
identical to
Port
A
except
that
it
is
selected
by
a
1
latched
from ADo
and
a
from AD1.
In
normal
operation,
an input high on
RESET
causes
all
pins
in
Ports
A
and
B
to
assume
input
mode
(clear
DDR
register).
When
the
Chip Enables
are active, a
low on IOR
will
output the selected
I/O port
onto
the
AD
bus.
IOR
low
performs
the
same
function as the
combinati
on
o
f
IO/M
high
and
RD
low.
When
IOR
is
not used
in
a
system,
IOR
should be
tied to
Vcc ("1").
+5
volt
supply.
Ground
Reference.
Vdd
is
a
programming
voltage,
and
must
be
tied to
+5V when
the
8755A
is
being
read.
For
programming,
a high voltage
is
supplied with
Vdd =
25V,
typical.
(See
section
on programming.)
6-60