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8048/8648/8748/8035
PIN
DESCRIPTION
Designation
Pin
#
Function
V
ss
20
Circuit
GND
potential
V DD
26
Programming power
supply;
+25V
during program,
+5V
during
oper-
ation
for
both
ROM
and
PROM.
Low
power
standby
pin
in
8048
and 8035L.
Vcc
40
Main power
supply;
+5V
during
operation
and programming.
PROG
25
Program
pulse
(+23V)
input
pin
during
8748
programming.
Output
strobe for
8243
I/O
expander.
8-bit
quasi-bidirectional port.
P10-P17
27-34
Port
1
P20-P27
21-24
Port
2
35-38
DB
-DB-
BUS
TO
T1
INT
8-bit
quasi-bidirectional
port.
P20-P23
contain the four high
order
program
counter
bits
during
an external
program
memory
fetch
and
serve as
a
4-bit
I/O
expander
bus
for
8243.
12-19
True
bidirectional
port
which
can
be written
or
read
synchronously
using
the
RD,
WR
strobes.
The
port
can
also
be
statically latched.
Contains the 8 low order
program
counter
bits
during
an
external
program
memory
fetch,
and
receives
the addressed instruction
under
the
control of
PSEN.
Also contains the
address
and
data during
an
external
RAM
data
store
instructi
on,
u
nder
control of
ALE, RD,
and
WW.
1
Input
pin testable using the con-
ditional transfer instructions
JT0
and JNT0.
TO
can be designated
as
a
clock
output
using
ENT0 CLK
instruction.
TO
is
also
used during
programming.
39
Input
pin testable using the
JT1,
and
JNT1
instructions.
Can
be
des-
ignated the
timer /counter input
using
the
STRT CNT
instruction.
6
Interrupt input.
Initiates
an
inter-
rupt
if
interrupt
is
enabled.
Inter-
rupt
is
disabled
after
a reset.
Also
testable
with conditional
jump
instruction. (Active
low)
Designation
Pin
#
Function
RD
RESET
WR
ALE
PSEN
SS
EA
XTAL1
XTAL2
8
Output
strobe activated
during
a
BUS
read.
Can be
used to enable
data
onto
the
bus
from
an
external
device.
Used
as a
read strobe to external
data
memory.
(Active low)
4
Input
which
is
used
to
initialize
the
processor.
Also used during
PROM
programming
verification,
and
power down.
(Active low)
(Non
TTL
V,
H
)
10
Output
strobe during
a
bus
write.
(Active low)
Used
as
write strobe to external
data
memory.
1
Address
latch
enable.
This
signal
occurs
once
during each
cycle
and
is
useful as
a
clock output.
The
negative
edge
of
ALE
strobes
address
into
external data
and
pro-
gram memory.
9
Program
store enable.
This
output
occurs only during
a
fetch to
exter-
nal
program
memory.
(Active low)
5
Single step input
can be used
in
con-
junction
with
ALE
to "single
step"
the processor
through each
in-
struction. (Active
low)
7
External access input
which
forces
all
program
memory
fetches to
re-
ference external
memory.
Useful
for
emulation and debug, and
essential for testing
and program
verification.
(Active high)
2
One
side
of
crystal
input
for
inter-
nal oscillator.
Also input
for exter-
nal
source.
(Non
TTL
Vih
)
3
Other
side
of
crystal input.
6-2
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