Intel MCS48 User Manual page 291

I®
my
OOCHA
*^
8251
A
PROGRAMMABLE
COMMUNICATION
INTERFACE
Synchronous and Asynchronous
Operation
Synchronous
5-8 Bit Characters;
Internal or External Character Synchro-
nization;
Automatic Sync
Insertion
Asynchronous
5-8 Bit Characters;
Clock
Rate—
1,
16
or
64
Times Baud
Rate;
Break Character
Generation;
1,
1
1
/2,
or 2 Stop
Bits;
False
Start
Bit
Detection;
Automatic Break
Detect
and
Handling.
Synchronous Baud
Rate
—
DC
to
64K
Baud
Single
TTL
Clock
The
Intel®
8251 A
is
the enhanced
version
of the industry standard,
Intel®
8251
Universal
Synchronous/Asynchronous
Receiver/Transmitter (USART),
designed
for
data
communications
with
Intel's
new
high performance
family
of
microprocessors such as
the 8085.
The
8251
A
is
used as
a peripheral device
and
is
programmed
by the
CPU
to
operate
using
virtually
any
serial
data transmission technique presently
in
use
(including
IBM
"bi-sync").
The
USART
accepts
data characters from the
CPU
in parallel
format and
then converts
them
into
a continuous
serial
data stream
for
transmission. Simultaneously,
it
can receive
serial
data streams and
convert
them
into parallel data characters
for the
CPU. The
USART
will
signal the
CPU
whenever
it
can accept a new
character
for
transmission
or
whenever
it
has
received a character
for the
CPU. The
CPU
can
read the complete
status
of
the
USART
at
any
time.
These
include data
transmission
errors
and
control signals
such
as
SYNDET, TxEMPTY.
The
chip
is
constructed using N-channel
silicon
gate technology.
Asynchronous Baud
Rate
—
DC
to
19.2K
Baud
Full
Duplex,
Double
Buffered, Trans-
mitter
and
Receiver
Error
Detection
—
Parity,
Overrun
and
Framing
Fully
Compatible
with 8080/8085
CPU
28-Pin
DIP Package
All
Inputs
and Outputs
are
TTL
Compatible
Single
+
5V Supply
PIN
CONFIGURATION
7
8251
A
22
PIN
NAMES
BLOCK
DIAGRAM
I
RESET
-
-
CLK
READ'WRITE
C D_
».
CONTROL
RD
—o
LOGIC
WR_
»-o
5
Dv D
Data Bus
(8
bits)
C/D
Control
or Data
is
co be Written
or
Read
RD
Read Data
Command
WR Write Data
or Control
Command
CS
Chip Enable
CLK
Clock
Pulse
ITTLI
RESET
Reset
TxC
Transmitter Clock
TxD
Transmitter Data
RxC
Receiver Clock
RxD
Receiver Data
RxRDY
Receiver
Ready
lhas character for
8080)
TxRDY
Transmitter
Ready
(ready
for char
from 8080)
I
DSR
DTR^._
CTS-
RTS
.
J.
TRANSMIT
BUFFER
(P-S)
.TxRDY
-TxE
_TxC
RECEIVE
BUFFER
(S-P)
RECEIVE
CONTROL
.H«RDY
rTc
.
SYNDET
^NTE^G^Ato!?
U79
$
^
RESP0NSB,LITY F0R
THE "^ 0F ANY
CKmm
0THER THAN
CKmm
EMB0DIED
IN
*
N
INTEL
P "°<MT. NO
OTHER CIRCUIT PATENT
LICENSES ARE
IMPLIED.
8-1
002 16A