Intel MCS48 User Manual page 224

8155/8156/8155-2/8156-2
TABLE
1.
TABLE OF PORT CONTROL
ASSIGNMENT.
Pin
ALT1
ALT
2
ALT
3
ALT
4
PCO
Input Port
Output
Port
A
INTR
(Port
A
Interrupt)
A
INTR
(Port
A
Interrupt)
PC1
Input Port
Output
Port
A
BF
(Port
A
Buffer
Full)
A
BF
(Port
A
Buffer
Full)
PC2
Input Port
Output
Port
A STB
(Port
A
Strobe)
A STB
(Port
A
Strobe)
PC3
Input Port
Output
Port
Output
Port
B INTR
(Port
B
Interrupt)
PC4
Input Port
Output
Port
Output
Port
B BF
(Port
B
Buffer
Full)
PC5
Input Port Output
Port
Output
Port
B
STB
(Port
B
Strobe)
Note
in
the
diagram
that
when
the I/O ports are pro-
grammed
to
be output
ports,
the contents
of the
output
ports
can
still
be read by
a
READ
operation
when
appro-
priately
addressed.
The
outputs
of the
8155/8156
are
"glitch-free"
meaning
that
you can
write a "1" to
a
bit
position that
was
previ-
ously
"1
"
and
the
level at the
output
pin
will
not
change.
Note
also that the
output
latch
is
cleared
when
the port
enters the input
mode. The
output
latch
cannot be loaded
by
writing to the port
if
the port
is in
the input
mode. The
result
is
that
each time
a port
mode
is
changed from
input
to output, the output pins
will
go
low.
When
the
8155/56
is
RESET,
the output
latches are
all
cleared
and
all
3 ports
enter the input
mode.
When
in
the
ALT
1
or
ALT
2
modes,
the
bits
of
PORT
C
are structured
like
the
diagram above
in
the
simple
input
or output
mode,
respectively.
Reading from an
input port with nothing
connected
to
the
pins
will
provide unpredictable
results.
Figure 7
shows
how
the
8155/8156
I/O ports might be
configured
in
a
typical
MCS-85
system.
8155/8156
PORT
C
>'
TO
8085
RST INPUT
OUTPUT > PORT A
A
INTR (SIGNALS
DATA
RECEIVED)
A
BF (SIGNALS
DATA
READY!
A STB (ACKNOWL.
DATA
RECEIVED)
B
STB (LOADS PORT
B
LATCH)
B BF (SIGNALS
BUFFER
IS
FULL)
B
INTR (SIGNALS
BUFFER
A
READY FOR READING)
C
INPUT
\
TO/FROM
PERIPHERAL
INTERFACE
TO
8085
INPUT
PORT
(OPTIONAL)
TO 8085 RST INPUT
Figure
7.
Example:
Command
Register
=
00111001
6-72