Intel MCS48 User Manual page 25

INTRODUCTION
three
levels of
subroutines
may
be
ac-
commodated.
Instruction Register
and Decoder
Every
computer
has a
Word
Length
that
is
characteristic of that
machine.
A
computer's
word
length
is
usually
determined by
the
size
of
its
internal
storage
elements and
intercon-
necting paths
(referred to
as Buses);
for
example, a
computer
whose
registers
and
buses
can
store
and
transfer 8-bits of
information has a
characteristic
word
length
of 8-bits
and
is
referred to as
an
8-bit parallel
processor.
An
8-bit parallel
processor gener-
ally
finds
it
most
efficient to
deal with
8-bit
binary
fields,
and
the
memory
associated
with
such
a processor
is
therefore
organized
to store 8-bits
in
each
addressable
memory
location.
Data and
instructions
are stored
in
memory
as
8-bit
binary
numbers,
or as
numbers
that
are
integral multiples of
8-bits:
16-bits, 24-bits,
and
so
on.
This
characteristic
8-bit field
is
often referred to
as a
Byte.
If
however,
efficient
handling
of
4
or
even
1-bit
data
is
necessary
special
processor
instruc-
tions
can
provide
this capability.
Each
operation
that
the processor can
perform
is
identified
by a unique
byte
of
data
known
as an
Instruction
Code
or
Operation
Code.
An
8-bit
word
used
as
an
instruction
code can
distinguish
between 256
alternative
actions,
more
than adequate
for
most
processors.
The
processor fetches
an
instruction
in
two
distinct
operations.
First,
the processor
transmits the
address
in
its
Program Counter
to
the
program memory. Then
the
program
memory
returns the
addressed
byte
to
the
processor.
The
CPU
stores
this
instruction
byte
in
a
register
known
as the
Instruction
Register,
and
uses
it
to direct
activities
during
the remainder
of
the instruction execution.
The
8-bits
stored
in
the
instruction register
can be decoded and
used
to selectively
activate
one
of
a
number
of
output
lines.
Each
line
represents a
set of
activities
associated
with
execution
of
a
particular instruction
code.
The
enabled
line
can be
combined
with
selected timing
pulses, to
develop
electrical
signals that
can
then
be used
to
initiate
specific actions.
This
translation of
code
into
action
is
performed by
the Instruction
Decoder and
by
the associated
control
circuitry.
An
8-bit instruction
code
is
often
sufficient
to
specify a
particular
processing
action.
There
are times,
however,
when
execution
of the
instruction requires
more
information than
8-
bits
can
convey.
One
example
of
this
is
when
the
instruction
references
a
memory
location.
The
basic
instruction
code
identifies
the operation
to
be
performed, but cannot specify the object
address as
well. In
a case
like this,
a
two
byte
instruction
must
be used. Successive
instruc-
tion
bytes are stored
in
sequentially
adjacent
memory
locations,
and
the processor
per-
forms
two
fetches
in
succession
to
obtain the
full
instruction.
The
first
byte
retrieved
from
memory
is
placed
in
the processor's
instruc-
tion register,
and subsequent
byte
is
placed
in
temporary
storage;
the processor then
proceeds
with the execution phase.
Address
Register(s)
A CPU
may
use
a register to hold the
address
of
a
memory
location that
is
to
be accessed
for data.
If
the address
register
is
Program-
mable,
(i.e.,
if
there are
instructions that
allow
the
programmer
to
alter
the contents
of
the
register)
the
program can
"build"
an address
in
the
address
register prior to
executing a
Memory
Reference
instruction
(i.e.,
an
instruction that
reads data from
memory,
writes data to
memory
or operates
on
data
stored
in
memory).
Arithmetic/Logic Unit
(ALU)
All
processors contain an
arithmetic/logic
unit,
which
is
often referred to simply as the
ALU. The ALU,
as
its
name
implies,
is
that
portion of
the
CPU
hardware which performs
the arithmetic
and
logical
operations
on
the
binary
data.
The
ALU
must
contain
an
Adder which
is
capable
of
combining
the contents of
two
registers
in
accordance
with the
logic of
binary
arithmetic. This
provision permits the
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