Intel MCS48 User Manual page 336

8259A
PROGRAMMING
THE
8259A
The 8259A
accepts two
types
of
command
words
gener-
ated by the
CPU:
1.
Initialization
Command
Words
(ICWs): Before normal
operation can
begin,
each 8259A
in
the
system must
be brought
to a starting point
—
by a
sequence
of 2 to
4
bytes timed by
WR
pulses. This
sequence
is
described
in
Figure
1.
2.
Operation
Command
Words
(OCWs): These
are the
command
words which
command
the
8259A
to oper-
ate
in
various
interrupt
modes. These modes
are:
a.
Fully
nested
mode
b.
Rotating
priority
mode
c.
Special
mask mode
d.
Polled
mode
INITIALIZATION
GENERAL
Whenever
a
command
is
issued with
AO = and D4 =
1
,
this
is
interpreted as
Initialization
Command
Word
1
(ICW1).
ICW1
starts the
initialization
sequence
during
which
the following automatically occur.
a.
The
Interrupt
Mask
Register
is
cleared.
b.
IR 7 input
is
assigned
priority
7.
c.
The
slave
mode
address
is
set to
7.
d.
Special
Mask Mode
is
cleared
and
Status
Read
is
set to
IRR.
e.
If
IC4
=
0,
then
all
functions selected
in
ICW4
are set to
zero.
(Non-Buffered mode*, no
Auto-EOI,
MCS-80/85
system, non
SFNM
.
The
OCWs
can be
written into the
8259A
anytime
after
initialization.
'Not*: Master/Slave
in
ICW4
is
only used
in
the buttered mode.
Ao
04
D
3
RD
WR
cs
INPUT
OPERATION
(READ)
1
1
1
IRR, ISR or Interrupting
Level—
»-DATA BUS
(Note
1)
IMR-^DATA
BUS
OUTPUT OPERATION
(WRITE)
1
1
X
1
X
X
1
1
1
1
DATA BUS -»*OCW2
DATA BUS-»-OCW3
DATA BUS
-ICWI
DATA BUS-**OCW1,
ICW2, ICW3,
ICW4
(Note
2)
DISABLE
FUNCTION
X
X
X
X
X
X
1
X
1
X
1
DATA BUS
—
3-STATE (NO
OPERATION)
DATA BUS
—
3-STATE (NO
OPERATION)
Not**:
1
Selection
of
IRR, ISR or Interrupting Level
is
based on
the
content
of
OCW3
written before the
READ
operation.
2
On-chip sequencer
logic
queues these
commands
into
proper
sequence
8259A Basic Operation
8-46