Intel MCS48 User Manual page 310

intel
8255A/8255A-5
PROGRAMMABLE
PERIPHERAL INTERFACE
MCS-85™
Compatible 8255A-5
24
Programmable
I/O
Pins
Completely
TTL
Compatible
Fully
Compatible
with
Intel® Micro-
processor
Families
Improved Timing
Characteristics
Direct
Bit
Set/Reset
Capability
Easing
Control Application
Interface
40-Pin
Dual
In-Line
Package
Reduces System Package Count
Improved
DC
Driving Capability
The
Intel®
8255A
is
a general
purpose programmable
I/O
device
designed
for
use
with
Intel®
microprocessors.
It
has
24
I/O
pins which
may
be
individually
programmed
in
2
groups
of 12
and used
in
3
major
modes
of operation.
In
the
first
mode (MODE
0),
each group
of
12
I/O
pins
may
be
programmed
in
sets of 4 to be input or output.
In
MODE
1,
the
second
mode, each group
may
be
programmed
to
have 8
lines of
input or output.
Of
the
remaining
4
pins,
3 are
used
for
hand-
shaking and
interrupt
control signals.
The
third
mode
of
operation
(MODE
2) is
a bidirectional
bus
mode
which uses 8
lines for
a
bidirectional bus,
and
5
lines,
borrowing
one from
the other group,
for
handshaking.
PIN
CONFIGURATION
PA3 C
W^
40
~
PA2
C.
39
-|
PAlC
38
I
PAO
C
37
Z
RD
£
36
Z
cs
C. 6 35
z
GND
G
34
z
*'C
8 33
z
ao r
9 32
z
PC7
Q
PC6Q
10
8255A
31
30
E;
PC5
C
12
29
-
PC4
fj
28
pcoC
14 27
n
pci C 15
26
n
PC2 C 16
25
Z
PC3 Q
24
Z
PBOQ
18
J
PB1
C
19
22
3
PP.2C
20 21 z
PIN
NAMES
8255A
BLOCK DIAGRAM
N V
HiiMiN
,z:
c
c=^
D
7-°0 DATA
BUS
(Bl
DIRECTIONAL)
RESET RESET
INPUT
a
CHIP SELECT
RD READ
INPUT
WR
WRITE INPUT
AO.
A1
PORT ADDRESS
PA7PA0 PORT A
(BIT)
PB7PB0 PORT
B
(BIT)
«c7*co PORT
C
(BIT)
Vcc
6
VOLTS
OND
9
VOLTS
z
c
e=>
:h c
c=^>
f
C=>;»
C>
:£:
$x
INTEL
CORPORATION ASSUMES
NO
RESPONSIBILITY
FOR THE USE Of ANY CIRCUITRY
OTHER THAN
CRCWTRY EMBODIED
IN
AN
INTEL PRODUCT. NO OTHER
CIRCUIT
PATENT LICENSES ARE
IMPLIED.
©
INTEL
CORPORATION, 1979
8-20