Intel MCS48 User Manual page 261

5101
FAMILY
Low Vec
Data Retention
Waveform
Typical
IcCDR Vs.
Temperature
SUPPLY
VOLTAGE
(V cc
)
CHIP ENABLE
(CE2)
®
4.75V
©
V
DR
®
V, H
®
0.2V
I
!
i
Vcc
=
2V
Vw
= 2V
i
\S
i
j
i i
20 30 40 50
TEMPERATURE
(°C)
A.C. Characteristics
T A
= 0°C
to 70°C,
V
CC
=
5V
±5%,
unless
otherwise
specified.
READ CYCLE
Symbol
Parameter
5101 L-1
Limits
(ns)
Min.
Max.
5101
Land
5101L-3
Limits
(ns)
Min.
Max.
tRC
Read
Cycle
450 650
tA
Access
Time
450 650
t-coi
Chip Enable (CE
1)
to
Output 400 600
tC02
Chip Enable (CE
2)
to
Output 500 700
tOD
Output
Disable to Output 250
350
tDF
Data
Output
to
High
Z
State
130 150
tOH1
Previous
Read
Data Valid with
Respect
to
Address Change
tOH2 Previous
Read
Data
Valid
with
Respect
to
Chip
Enable
WRITE CYCLE
t-wc
Write Cycle 450 650
*AW
Write
Delay
130 150
tcwi
Chip Enable
(CE~1)
to
Write
350 550
T-CW2
Chip
Enable
(CE
2)
to
Write 350 550
tow
Data Setup 250 400
t-DH
Data Hold
50 100
t-WP
Write Pulse
250 400
t-WR
Write
Recovery
50 50
*DS
Output
Disable
Setup 130
150
A.
C.
CONDITIONS OF TEST
Input Pulse
Levels:
+0.65
Volt
to 2.2
Volt
Input Pulse Rise and
Fall
Times: 20nsec
Timing Measurement
Reference
Level:
1.5
Volt
Output
Load:
1
TTL
Gate and C
L
-
100pF
NOTES:
1.
Typical values are for
T
A
= 25°
C
and nominal
supply
voltage.
2.
This
parameter
is
periodically
sampled and
is
not
100%
tested.
Capacitance
2
r
25
C,
f
=
1MHz
Symbol
Test
Limits (pF)
Typ. Max.
C|N
Input Capacitance
(All
Input
Pins) V,
N
=
0V
4 8
Cqut
Output
Capacitance Vqut
=
0V
8
12
7-23