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8049/8039/8039-6
PIN
DESCRIPTION
Designation
Pin#
Function
Vss
20
Circuit
GND
potential
Vdd
26
+5V
during operation.
Low
power
standby
pin.
v
C c
40
Main power
supply;
+5V
during
operation.
PROG
25
Output
strobe for
8243
I/O
expander.
P10-P17
Port
1
27-34
8-bit
quasi-bidirectional port.
P20-P27
Port
2
21-24
35-38
8-bit
quasi-bidirectional port.
P?f)-P93
mntain
thp
fr>ur
hinh
Designation
Pjn
#
Function
RD
D0-D7
BUS
TO
T1
INT
order
program
counter
bits
during
an external
program
memory
fetch
and
serve as
a 4-bit
I/O
expander
bus
for
8243
12-19
True
bidirectional
port
which
can
be written
or read
synchronously
using
the
RD,
WR
strobes.
The
port
can
also
be
statically latched.
Contains the 8
low
order
program
counter
bits
during
an
external
program
memory
fetch,
and
receives
the addressed instruction
under
the
control of
PSEN.
Also contains the
address
and
data during
an
external
RAM
data
store
instructi
on, u nder
control of
ALE, RD,
and
WW.
1
Input pin
testable
using the con-
ditional transfer instructions
JT0
and
JNT0.
TO
can be
designated
as
a
clock
output
using
ENT0 CLK
instruction.
39
Input
pin testable using
the JT1,
and
JNT1
instructions.
Can
be
des-
ignated the timer /counter input using
the
STRT CNT
instruction.
°
Interrupt input.
Initiates
an
inter-
rupt
if
interrupt
is
enabled.
Inter-
rupt
is
disabled
after a
reset.
Also
testable
with conditional
jump
instruction.
(Active low)
RESET
WR
ALE
PSEN
SS
EA
XTAL1
XTAL2
8
Output
strobe activated
during
a
BUS
read.
Can
be used
to
enable
data
onto
the
BUS
from
an
external
device.
Used
as
a
Read
Strobe
to External
Data
Memory.
(Active
low)
4
Input
which
is
used
to
initialize
the
processor.
Also used during
verifi-
cation,
and power down.
(Active
low)
(NonTTL
V|
H
)
10
Output
strobe during
a
BUS
write.
(Active low)
Used
as
write strobe
to External
Data
Memory.
11
Address
Latch Enable. This
signal
occurs
once
during each cycle
and
is
useful as
a
clock output.
The
negative
edge
of
ALE
strobes
address
into
external data
and
pro-
gram memory.
9
Program
Store Enable. This
output
occurs only during
a
fetch to
exter-
nal
program
memory.
(Active low)
5
Single step input
can be used
in
con-
junction
with
ALE
to "single
step"
the processor
through each
in-
struction. (Active
low)
7
External
Access
input
which
forces
all
program
memory
fetches to
re-
ference external
memory.
Useful
for
emulation and debug,
and
essential for testing
and program
verification.
(Active high)
2
One
side
of
crystal
input
for
inter-
nal oscillator.
Also input
for exter-
nal
source.
(Not
TTL
Compatible)
3
Other
side
of
crystal input.
6-29
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