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8041A/8741A
UPI-41
UPI-41A
5.
P26
and
P27 are port pins
only.
If
"EN
FLAGS"
has been
executed,
P
2
5
becomes
the
IBF
(Input
Buffer
Full)
pin.
A
"1"
written to
P
25
enables
the IBF
pin (the pin
outputs the
inverse of the
IBF Status
Bit).
A
"0"
written to
P
2 5
disables the
fBT
pin (the pin
remains
low).
This
pin
can be used
to
indi-
cate
that
the UPI-41
is
ready
for data.
r^n
—
^
—
'
—
^~
n^i—
r-d-^"
-
|
P24
H
P25
-OBF
(INTERRUPT REQUEST)
IBF
(INTERRUPT REQUEST)
DATA BUS BUFFER
INTERRUPT
CAPABILITY
EN FLAGS
Op
Code:
0F5H
1
D
7
D„
P
2 6
and P
2 7
are
port
pins or
DMA
handshake
pins
for
use
with
a
DMA
controller.
These
pins default
to port
pins
on
Reset.
If
the
"EN
DMA"
instruction
has
been
executed,
P
2
6
becomes
the
DRQ
(DMA
ReQuest)
pin.
A
"1"
written
to
P
26
causes
a
DMA
request
(DRQ
is
activated).
DRQ
is
deactivated by
DACK
•
RD,
DACK
•
WR,
or
execution
of
the
"EN
DMA"
instruction.
If
"EN
DMA"
has been executed,
P
27
becomes
the
DACK
(DMA
ACKnowledge)
pin.
This
pin
acts as a
chip select input
for
the
Data
Bus
Buffer
registers
during
DMA
transfers.
8041
A/
8741
A
DRQ
P26
DACK
P27
O*
O
DACK
DMA HANDSHAKE
CAPABILITY
EN
DMA
Op
Code:
0E5H
10
D1
°0
8-114
00 188
A
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