Intel MCS48 User Manual page 400

intel
8294
DATA ENCRYPTION
UNIT
Certified
by
National Bureau
of
Standards
80 Byte/Sec Data Conversion Rate
64-Bit
Data Encryption Using
56-Bit
Key
7-Bit
User Output
Port
Single
5V
± 10%
Power
Supply
Peripheral to
MCS-86
T
*
MC8*85™,
MCS-80™
and
MCS-48™
Processors
DMA
Interface
3
Interrupt
Outputs
to
Aid
in
Loading
and
Unloading Data
Implements
Federal Information
Processing Data Encryption Standard
Encrypt
and
Decrypt
Modes
Available
DESCRIPTION
The
Intel® 8294 Data Encryption
Unit
(DEU)
is
a microprocessor
peripheral device designed
to
encrypt and decrypt
64-bit
blocks
of
data using the algorithm
specified
in
the Federal Information
Processing Data Encryption Standard.
The
DEU
operates on
64-bit text
words
using a
56-bit
user-specified key
to
produce
64-bit
cipher words.
The
operation
is
reversible:
if
the cipher word
is
operated upon,
the
original text
word
is
produced. The
algorithm
itself is
perma-
nently contained
in
the 8294;
however, the
56-bit
key
is
user-defined and
may
be
changed
at
any
time.
The
56-bit
key
and
64-bit
message
data
are transferred
to
and from
the 8294
in
8-bit
bytes by
way
of the
system
data
bus.
A
DMA
interface
and
three
interrupt
outputs
are available to
minimize software overhead associated
with data
transfer. Also, by using the
DMA
interface
two
or
more
DEUs may
be operated
in parallel to
achieve
effective
system
conversion
rates
which
are
virtually
any
multiple
of
80
bytes/second.
The
8294
also
has a
7-bit
TTL
compatible output
port
for
user-specified functions.
Because
the 8294 implements
the
NBS
encryption algorithm
it
can be used
in
a
variety of Electronic
Funds
Transfer
applications as
well as other
electronic
banking and data
handling applications where
data
must
be encrypted.
PIN
CONFIGURATION
PIN
NAMES
BLOCK DIAGRAM
NCC
1
XI
C
2
X2C
3
RESET C 4
NCC
5
CSC
6
GNDC
7
RDC
8
AOC
9
WRC
II
SYNCC
DOC
D1C
D2C
D3C
D4C
D5C
D6C
D7C
GNDC
3VCC
3NC
3DACK
3DRQ
DSRQ
DOAV
3NC
3P6
3P5
3P4
3P3
DP2
DPI
DPO
DVDD
DNC
3CCMP
DNC
3NC
3NC
PIN
NAME
FUNCTION
D7D0 DATA BUS
RD.WR
READ.WRITE
STROBES
CS
CHIP SELECT
Ao
CONTROL/DATA SELECT
RESET RESET
INPUT
X,,X
2
FREQUENCY REFERENCE
INPUT
SYNC
HIGH FREQUENCY OUTPUT
DRQ.DACK DMA
REQUEST.DMA
ACKNOWLEDGE
SRQ,OAV,CCMP INTERRUPT REQUEST OUTPUTS
P
6
Po
OUTPUT PORT
LINES
Vcc.Vdd.gnd + 5V
POWER.GND
NC NO CONNECTION
&
SRQ-^-
OAV-»-
CCMP--
RESET-
SYNC-
POWER -
GND-
DATA
BUS
BUFFER
REGISTERS
CONTROL
AND
INTERRUPT
LOGIC
>
KEY
BUFFER
STORAGE
A
ALGORITH
-y
TABLE
7-bit
OUTPUT
PORT
-DRQ
-DACK
INTEL
CORPORATION ASSUMES NO
RESPONSIBILITY
FOR THE USE OF ANY CIRCUITRY
OTHER THAN
CIRCUITRY
EMBODIED
IN
AN
INTEL PRODUCT.
NO OTHER
CIRCUIT
PATENT LICENSES ARE
IMPLIED.
©
INTEL
CORPORATION, 1979
8-110
00230A