Single Component - Intel MCS48 User Manual

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M8048/M8748/M8035
SINGLE
COMPONENT
8-BIT
MICROCOMPUTER
*8048
Mask Programmable
ROM
*8748 User Programmable/Erasable
EPROM
*8035
External
ROM
or
EPROM
-55°
C
to
+125°C
Operation
(M8048/M8035L)
-55°
C
to
+100°C
Operation
(M8748/M8035)
8-Bit
CPU,
ROM, RAM,
I/O
in
Single
Package
Interchangeable
ROM
and
EPROM
Versions
Single
5V Supply
2.5
psec and
5.0
Msec Cycle
Versions
All
Instructions
1
or 2 Cycles.
Over
90
Instructions:
70%
Single
Byte
1K
x
8ROM/EPROM
64
x
8
RAM
27 I/O Lines
Interval
Timer/Event Counter
Easily
Expandable
Memory
and
I/O
Compatible
with 8080/8085 Series
Peripherals
Single Level Interrupt
The
Intel®
M8048/M8748/M8035/M8035L
is
a totally self-sufficient 8-bit parallel
computer
fabricated
on a single
silicon
chip using
Intel's
N-channel
silicon gate
MOS
process.
The M8048
contains a
1K
x
8
program memory,
a
64 x 8
RAM
data
memory,
27 I/O
lines,
and an
8-bit
timer/counter
in
addition to
on-board
oscillator
and
clock
circuits.
For systems
that
require extra
capability,
the
M8048
can be expanded
using standard
memories and MCS-80 T 7MCS-85 T
"
peripherals.
The M8035
is
the equivalent
of
an
M8048
without
program
memory. The M8035L
has
the
RAM
power
down mode
of the
M8048
while the
M8035
does
not.
To
reduce development
problems
to a
minimum
and
provide
maximum
flexibility,
three
interchangeable pin-compatible* versions
of this
single
component microcomputer
exist: the
M8748
with
user-programmable and
erasable
EPROM
program
memory
for
prototype and preproduction systems,
the
M8048
with
factory-programmed
mask
ROM
program
memory
for
low
cost,
high
volume
production,
and
the
M8035
without
program
memory
for
use with external
program
memories.
This microprocessor
is
designed
to
be an
efficient controller as well as
an arithmetic processor.
The M8048
has extensive
bit
handling
capability as well as
facilities for
both binary and
BCD
arithmetic. Efficient
use
of
program
memory
results
from an
instruction set consisting mostly
of
single byte instructions
and no
instructions
over
2 bytes
in
length.
PIN
CONFIGURATION
TOC
XTAL iC
2 39
XTAL 2[
3
38
RESET
C
4
37
SSC
5 36
INtC
6 35
EAC
7
34
RbC
8
33
psenC
9
M8048
32
wrC
10
M8748
31
aleC
11
M8035
30
DB„C
12 29
DB, £
13 28
DB,C
14 27
OBjC
15
26
DB
4
C 16 25
OB5C
17
24
DB
6
[I
18
23
DB,C
19
22
LOGIC
SYMBOL
D
v
cc
D
T
'
]P27
XTAL-
!]P26
DP25
]P24
RESET
HP17
single
DP16
step
I)P15 EXTERNAL
UP14
MEM
IJP13
DP12
TEST-
DPIl
I]pio
I]v
DD
INTERRUPT
^ PROG
jnz
HP22
UP21
bus
C
DP20
<X>"
RT
PROGRAM
-STORE
ENABLE
ADDRESS
-LATCH
ENABLE
PORT
-EXPANDER
STROBE
BLOCK DIAGRAM
1024
WORDS
PROGRAM
MEMORY
7^
iz
8
BIT
TIMER/
EVENT COUNTER
64
WORDS
DATA
MEMORY
7^
\7
INTEL CORPORATION ASSUMES NO
RESPONSIBILITY
FOR
THE USE OF ANY CIRCUITRY OTHER THAN
CIRCUITRY
EMBODIED
IN
AN
INTEL PRODUCT.
NO
OTHER
CIRCUIT PATENT LICENSES ARE
IMPLIED
e
INTEL
CORPORATION, 1979 g^g