Intel MCS48 User Manual page 20

INTRODUCTION
the 8048's
instruction set
and
incorporates
several
new
features
critical in
low
cost
applications.
Even
with low
component
costs,
however, a
project
may
be
jeopardized
by
high develop-
ment and
rework
costs
resulting
from an
inflexible
production
design.
Intel
has solved
this
problem by
creating
two
pin-compatible
versions
of the
8048 microcomputer: the
8048
with
mask Programmable
ROM
pro-
gram memory
for
low
cost production
and
the 8748
with user
programmable and
erasable
EPROM
program
memory
for
prototype development.
The
8748
is
essen-
tially
a
single
chip
microcomputer
"bread-
board" which can be
modified over and over
again during development- and
pre-produc-
tion
then replaced by the low cost
8021*,
8048, or 8049
ROM
for
volume
production.
The
8748
provides a very easy
transition
from development
to
production
and
also
provides an easy vehiclefortemporaryfield
updates
while
new
ROMs
are being
made.
SPECIAL
FEATURES
SINGLE
5V
SUPPLY
40 PIN DIP
OR
28
PIN DIP
PIN
COMPATIBLE
ROM
AND EPROM
2.5,
5.0
AND
10.0
/xsec
CYCLE VERSIONS
ALL INSTRUCTIONS
1
OR
2
CYCLES
SINGLE STEP
8
LEVEL
STACK
2
WORKING
REGISTER
BANKS
LC,
XTAL,
OR EXTERNAL
FREQUENCY SOURCE
OPTIONAL CLOCK OUTPUT
POWER DOWN
STANDBY
MODE
To
allow the
MCS-48
to
solve a
wide range
of
problems and
to
provide
for future
expansion,
all
8048 and 8049
functions
have been
made
externally
expandable
using
either special
expanders
or
standard
memories and
peripherals.
An
efficient
low
cost
means
of
I/O
expansion
is
provided by
either the
8243
I/O
Expander
or
standard
TTL
or
CMOS
circuits.
The
8243 provides
16 I/O
lines
in
a 24
pin
package. For
sys-
tems
with large I/O requirements, multiple
8243s can be
used.
*The 8021
is
code
compatible but
1-2
For
such
applications as
Keyboards,
Dis-
plays,
Serial
communication
lines,
etc.
standard
MCS-80/85
peripheral
circuits
may
be added. Program and
data
memory
may
be
expanded
using standard
memories
or the
8355 and 8155
memories
that also
include
programmable
I/O lines
and
timing
functions.
For
applications
which
require a
more
custom
tailored interface,
the
8041 or 8741
Universal Peripheral Interface
(UPI-41)
devices
can be
used.
The
UPI-41 devices
are available
in
both
ROM
and
EPROM
versions
and
are
essentially slave
versions
of
the 8048/8748 which
are
designed
to
interface directly with
expandable
MCS-48
processors
and
provide
flexible intelligent
I/O
capability.
The
8041/8741 share
the
instruction set of the
MCS-48
family
of
processors.
The
8035 and
8039 are
an 8048
or
8049
respectively
without
internal
program
memory
that
allows the user
to
match
his
program
memory
requirements
exactly
by
using a wide
variety of external
memories.
The 8035 and 8039
allow the
user
to select
a
minimum
cost
system no
matter
what
his
program
memory
re-
quirements.
The 8035L
is
an 8035
with the
powerdown
mode
of
the 8048.
The MCS-48
processors are
designed
to
be
efficient control
processors as
well
as
arithmetic processors.
They
provide
an
instruction set
which allows the user
to
directly set
and
reset individual lines
within
its
I/O ports as well as
test
individual
bits
within the
accumulator.
A
large variety of
branch and
table
look-up instructions
make
these processors very
efficient
in
implementing standard
logic
functions.
Also, special attention
has
been
given
to
code
efficiency.
Over
70%
of
the
instruc-
tions are a single byte long
and
all
others
are only two
bytes long.
This
means many
functions requiring 1.5K
to
2.
OK
bytes
in
other
computers
may
very
well
be
com-
pressed
into
the
1K words
resident
in
the
8048
or
up
to
3K
to
4K
equivalent bytes
may
be
compressed
into
the 8049.
not pin
compatible with the 8748.