Intel MCS48 User Manual page 269

intel
8212
8-BIT
INPUT/OUTPUT
PORT
Fully Parallel 8-Bit
Data
Register
and
Buffer
Service
Request
Flip-Flop
for
Interrupt
Generation
Low
Input
Load
Current
—
.25mA
Max.
Three
State
Outputs
Outputs Sink 15
mA
3.65V
Output High Voltage
for
Direct Interface to 8008,
8080A, or
8085A
CPU
Asynchronous
Register Clear
Replaces
Buffers,
Latches
and
Multiplexers
in
Microcomputer Systems
Reduces System Package Count
The
8212 input/output port consists
of
an 8-bit latch with 3-state
output buffers
along with control
and
device selection
logic.
Also included
is
a service
request
flip-flop for
the generation
and
control of interrupts to
the microprocessor.
The
device
is
multimode
in nature.
It
can be used
to
implement latches,
gated
buffers
or multiplexers. Thus,
all
of the
principal peripheral
and
input/output functions
of
a
microcomputer system can be implemented
with
this
device.
PIN
CONFIGURATION
^*r~
ds
iC
1
24
J
V
CC
Mor
2 23
Hint
D
'iL 3
22
J
DI
8
do
iC 4 21
Jdo
8
D
.
2
r
5
20
Hdi
7
do
2
l
D
'
3
L
6
7
8212
19
18
Jdo
7
JDI
6
D0
3
L
8
17
d
D °
6
oi
4
r
9 16
3
DI
5
do„l
10
15
Ido,
stbT
11
14
JCLR
gndP
12
13
3
DS
2
PIN
NAMES
Dl, Die
DOvDOb
1
DATA
IN
1~bATAOUT
"
"~~
OSi
DS
2
DEVICE SELECT
MD
STB
J_MODE
^STROBE
INT
!
INTERRUPT
(ACTIVE LOW)
CLR
|
CLEAR
(ACTIVE LOW)
DEVICE SELECTIO
_\
[T>DS1-op-
V
[n>
ns?—
I
J
[T> MD
(T£> STB
—
.
LOGIC
DIAGRAM
SERVICE REQUEST
FF
\
N
[7X>^
L3>D.,-
rX>
Di 2-
[T>QI
3
-
[9>DI
4
-
[?6>DI
6
-
(18>DI
6
-
[20>DI
7
-
[22>D1
8
-
[T?>CLR-
DATA
LATO
-T)
^y°- iNTrn>
:tive
lowi
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•
^n"""
~i
OUTPUT
SUFFER
DO,
[4>
--[^4D0
2
[6>
-f-j--(^-|
D0
3^>
D0
4
fj£>
-
T
-J^-D0
5
[T|>
-[>+D0
6
[T7>
—
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8 [f?>
J
I
INTEL
CORPORATION ASSUMES NO RESTONSMUTV
FOR THE USE OF ANY
CIRCUITRY
OTHER THAN
CIRCUITRY
EMBODIED
IN
AN
INTEL
PRODUCT. NO OTHER
CIRCUIT
PATENT
LICENSES
ARE
IMPLIED.
©
INTEL CORPORATION, 1979
7-31