Intel MCS48 User Manual page 402

Family of single chip microcomputers
Hide thumbs Also See for MCS48:
Table of Contents

Advertisement

intel
8041 A/8741
A
UNIVERSAL PERIPHERAL INTERFACE
8-BIT
MICROCOMPUTER
8-Bit
CPU
plus
ROM, RAM,
I/O,
Timer
and Clock
in
a Single
Package
One
8-Bit
Status
and
Two
Data
Regis-
ters for
Asynchronous
Slave-to-Master
Interface
DMA,
Interrupt,
or Polled
Operation
Supported
1024 x
8
ROM/EPROM,
64
x 8
RAM,
8-Bit
Timer/Counter, 18
Programmable
I/O
Pins
Fully
Compatible
with
MCS-48™,
MCS-80™, MCS-85™, and
MCS-86™
Microprocessor
Families
Expandable
I/O
ROM
Power-Down
Capability
Single
5V
Supply
The
Intel®
8041A/8741A
is
a general purpose,
programmable
interface
device
designed
for
use
with
a
variety of
8-bit
microprocessor systems.
It
contains a low cost
microcomputer
with
program memory,
data
memory,
8-bit
CPU,
I/O
ports,
timer/counter,
and
clock
in
a single 40-pin
package.
Interface registers are
included
to
enable
the
UPI device
to
function
as a
peripheral controller
in
MCS-48™, MCS-80™, MCS-85™, MCS-86™,
and
other
8-bit
systems.
The
UPI-41
A™
has
1
K
words
of
program
memory
and 64 words
of
data
memory
on-chip.
To
allow
full
user
flexibility
the
program
memory
is
available
as.
ROM
in
the 8041
A
version or
as UV-erasable
EPROM
in
the 8741
A
version.
The
8741
A
and
the 8041
A
are
fully
pin
compatible
for
easy
transition
from
prototype
to
production
level
designs.
The
device
has two
8-bit,
TTL
compatible
I/O
ports
and two
test inputs. Individual port lines
can
function
as
either
in-
puts
or
outputs under software
control.
I/O
can be
expanded
with the
8243
device
which
is
directly
compatible and has
16
I/O lines.
An
8-bit
programmable
timer/counter
is
included
in
the UPI device
for
generating timing
sequences
or
counting
external inputs. Additional
UPI
features include: single
5V
supply,
low
power
standby
mode
(in
the 8041A),
single-step
mode
for
debug
(in
the
8741
A),
and
dual
working
register
banks.
Because
it's
a
complete microcomputer,
the
UPI provides
more
flexibility
for
the
designer than conventional
LSI
inter-
face devices.
It
is
designed
to
be an
efficient
controller
as
well
as an arithmetic processor. Applications include
key-
board scanning,
printer control,
display multiplexing
and
similar
functions
which
involve interfacing peripheral
devices
to
microprocessor systems.
PIN
CONFIGURATION
BLOCK DIAGRAM
Tod
1
XlC
2
X2d
3
BESETC
4
SSC
5
CSC
6
EAC
7
RoT
8
AoC
9
WBC
SYNCC
DoC
oi
C
02
H
D3C
D4E
05
C
D6C
07
C
VSSC
10
14
16
18
8041
A/
31
8741A
an
UVCC
HT1
3P27'6SCK
U
P26/0RO
3P25/iBF
^
P24/OBF
HP17
DP18
DP15
HP14
HP13
DP12
I]P11
HP10
Hvdo
Dprog
3P23
DP22
3P21
MASTER
SYSTEM
INTERFACE
7T
sr<±t4
ACCUMULATOR
]o
<=>
»
PROM PROGRAM
SUPPLY
..
+
5
SUPPLY
»
Q
ROUND
c=c>
I
MULTIPLEXER
[
c=#
RANDOM
ACCESS
MEMORY
PROM/ROM
PROGRAM
MEMORY
PORT
4-7
EXPANDER
INTERFACE
C=>!
CONDITIONAL
BRANCH
LOGIC
8-BIT
timer;
event
counter
INTEL
CORPORATION ASSUMES
NO
RESPONSIBILITY
FOR
THE USE
Of ANY
CIRCUITRY
OTHER THAN
CIRCUITRY
EMBODIED
IN
AN
INTEL
PRODUCT.
NO
OTHER
CIRCUIT
PATENT
LICENSES ARE
IMPLIED.
©
INTEL
CORPORATION, 1979
8-112
001
88A

Advertisement

Table of Contents
loading

Table of Contents