Intel MCS48 User Manual page 135

APPLICATION
EXAMPLES
Vcc
Vqd
Vss
XTAL
1
8049
8048
8748
8021*
8035
8039
8022*
P22
P23
P24
P25
P26
P27
DBO
DB1
DB2
DB3
DB4
DB5
DB6
DB7
ALE
PSEN PROG
WR RD
-i=-
74150
(24)
Normal
I/O port
is
used
to select
an address
for the
16-to-1 multiplexer.
The
output of
the
multiplexer
is
brought
into
a
test input.
Eight
inputs
could
be
added
with a
74LS151
8-to-1
multiplexer using the
same
structure.
Note:
If
external
program
memory
is
being
addressed, use
P24-P27
instead of
P20-P23.
*PIN
NUMBERS ARE DIFFERENT FOR
8021,
8022
ADDING
16
INPUT
LINES
+£
V
CfJD
40
26
20
Vcc Vdd
Vss
pm
27
XTAL1
ph
pi?
28
29
3
XTAL
2
P13
P14
PI'S
30
31
32
4
RESET
P16
P17
33
34
P?0
21
EA
8049
P21
22
23
8048
P23
24
SS
TO
8748
P24
P25
P26
P27
DBO
DB1
DB2
DB3
DB4
DB5
DB6
DB7
35
3(5
37
38
12
S~
14
6D
5D
4D
3D
2D
1D
6Q
5Q
40
3Q
2Q
10.
39
13
j—
13
T1
14
j-
11
74LS174
(16)
15
j—
6
6
INT
16
j—
4
17
r~
3
CLK
18
19
9
ALE
PSEN
PROG
WR
RD
11
9 25 10 8
The
latch
can be loaded
with the
OUTL
instruction. After the
latch
is
loaded
the
BUS
output
state
can be modified with the
ANL
BUS,
#
DATA
and
the
ORL
BUS, #
DATA. The
OUTL
generates
a
WR
strobe;
ANL
and
ORL
do
not.
In
this configuration
DB0-DB7
will
be
momentarily
disturbed while the external
latch
is
loaded.
ADDING
6
OUTPUT
LINES
5-15