Table Of Contents - Intel MCS48 User Manual

Family of single chip microcomputers
Hide thumbs Also See for MCS48:
Table of Contents

Advertisement

SYSTEM
There
are three
locations
in
of
special
importance:
LOCATION
from
location
0.
3
Activating the Interrupt input
processor
(if
interrupt
is
jump
to
subroutine
at
location
3.
7
A
timer/counter
interrupt resulting
from
timer/counter overflow
(if
enabled)
causes
a
jump
to
subroutine
at
location
7.
first
instruction to
in
location
0,
the
first
subroutine
is
stored
in
location
3,
and
the
first
word
of
a
timer/counter service
7.
Program
used
to
store
constants as
well
as
program
instructions. Instructions
such as
MOVP
and
MOVP3
allow
easy access
to
data "lookup"
tables.
is
organized
as
64
or
128
words
8-bits
wide.
indirectly
addressable through
two
RAM
Pointer Registers
which
reside
at
1
register array.
In
addition,
the
first
8 locations
(0-7)
array are
designated
as
and
are
directly
addressable by
several
instructions.
registers
are
more
easily
addressed, they
are usually
used
to
store
frequently
accessed
intermediate
results.
The
DJNZ
instruction
efficient
use
of
the
working
gram
loop
counters
by
register
in
a single
instruction.
By
executing
a
Register
Bank
tion
(SEL RB)
RAM
locations
designated as
the
working
registers
in
place
0-7
and
are then
able.
This
second bank
of
may
be used
as
an
extension
of
the
first
bank
or
reserved
for
use
during
interrupt
service
I
|
SELMBO
LOCATION
7
INTERRUPT
VECTORS
PROGRAM
HERE
LOCATION
3
-
EXTERNAL
INTERRUPT
VECTORS
PROGRAM
HERE
RESET
VECTORS
PROGRAM
HERE
MCS-48™
32x8
(96 x
8)
1
WORKING
REGISTERS
_R_T
*R0'
'
8
OR
USER
RAM
16x8
BANKO
WORKING
REGISTERS
DIRECTLY
ADDRESSABLE
WHEN BANK
1
ADDRESSED
INDIRECTLY
THROUGH
R1
OR
R0
(RO'OR RV)
DIRECTLY
ADDRESSABLE
WHEN BANK
IS
SELECTED
IN
ADDITION R0
OR
R1
(RO'OR RV)
MAY
BE
USED TO ADDRESS
256
WORDS
OF
EXTERNAL
RAM.
(
)
8049
only
DATA
MEMORY MAP
2-3

Advertisement

Table of Contents
loading

Table of Contents