Intel MCS48 User Manual page 311

8255A/8255A-5
8255A
FUNCTIONAL
DESCRIPTION
General
The 8255A
is
a
programmable
peripheral interface
(PPI)
device designed
for
use
in Intel®
microcomputer
systems.
Its
function
is
that of
a general
purpose
I/O
component
to interface peripheral
equipment
to
the
microcomputer system
bus.
The
functional configura-
tion of the
8255A
is
programmed
by the
system software
so
that
normally no
external logic
is
necessary to
inter-
face peripheral devices or structures.
Data
Bus
Buffer
This 3-state bidirectional 8-bit buffer
is
used
to interface
the
8255A
to
the
system data
bus.
Data
is
transmitted or
received
by
the buffer
upon
execution
of
input or
output
instructions by the
CPU. Control
words and
status
infor-
mation are also transferred
through the data bus
buffer.
Read/Write
and
Control Logic
The
function of
this
block
is
to
manage
all
of the internal
and external transfers of both Data and Control or Status
words.
It
accepts inputs
from
the
CPU
Address and Con-
trol
busses
and
in
turn, issues
commands
to
both
of the
Control Groups.
(CS)
Chip
Select.
A
"low" on
this
input pin
enables
the
com-
muniction between
the
8255A and
the
CPU.
(RD)
Read.
A
"low"
on
this
input pin
enables the
8255A
to
send
the
data or status information to
the
CPU
on
the
data bus.
In
essence,
it
allows the
CPU
to
"read from"
the
8255A.
(WR)
Write.
A "low" on
this
input pin
enables the
CPU
to write
data or control
words
into
the 8255A.
(A
and
A^
Port Select
and
Port
Select
1.
These input signals,
in
conjunction with the
RD
and
WR
inputs, control the
selection of
one
of
the three ports or the control
word
registers.
They
are
normally
connected
to the least
significant bits of
the
address bus
(A
and A^.
8255A
BASIC
OPERATION
A1
A RD
WR
CS
INPUT
OPERATION
(READ)
1
PORT A
=
DATA
BUS
1 1
PORT
B =>
DATA
BUS
1
1
PORT
C=>
DATA
BUS
OUTPUT OPERATION
(WRITE)
1
DATA
BUS
=»
PORT A
1 1
DATA
BUS
=»
PORT
B
1
1
DATA
BUS
=»
PORT
C
1
1
1
DATA
BUS
=-
CONTROL
DISABLE
FUNCTION
X X X X
1
DATA
BUS=>
3-STATE
1 1 1
ILLEGAL CONDITION
X
X
1
1
DATA
BUS
=»
3-STATE
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Figure
1.
8255A Block Diagram Showing
Data
Bus
Buffer
and Read/Write Control Logic Functions
8-21
00744A