Intel MCS48 User Manual page 399

8292
PIN
DESCRIPTION
Symbol
I/O
Pin No.
Function
Symbol
I/O
Pin No.
Function
D -D
7
I/O
12-19
I
9
CS
I
6
RD
I
8
WR
I
10
RESET
I
4
DAV
I/O
37
ATNI
22
CIC
O
31
EOi
I/O
34
IFC
I/O
23
SYC
I
24
OBFI
O
35
IBFI
O
36
8 bidirectional lines
used
for
com-
munication
between
the central
processor
and
the 8292's
data
bus
buffers
and
status register.
Address
Line— Used
to
select
be-
tween the data
bus and
the status
register
during read
operations
and
to
distinguish
between
data
and
commands
written into the
8292 during write operations.
Chip
Select
Input— Used
to
select
the
8292 from other devices
on
the
common
data bus.
I/O
write input
which
allows the
master
CPU
to
write
to
the 8292.
I/O
read input
which allows the
master
CPU
to
read
from
the 8292.
Used
to
initialize
the chip to a
known
state during
power
on.
DAV
Handshake Line— Used
only
during
parallel poll,
configures to
force the
8291
to
accept the
paral-
lel
poll
status
bits.
Attention
In—
Used
by the 8292
to
monitor the
GPIB
ATN
control
line.
It
is
used during "take control
syn-
chronously" execution
and
during
the transfer control procedure.
Controller
In
Charge—
Controls
the
S/R
input of
the
SRQ
bus
trans-
ceiver.
It
can
also
be used
to
in-
dicate that
the
8292
is in
charge
of
the bus.
End Or
Identify—
One
of
the
GPIB
management
lines,
as defined by
IEEE
Std.
488-1975.
Used
with
ATN
as Identify
Message
during paral-
lel
poll.
Interface
Clear—
One
of
the
GPIB
management
lines,
as defined by
IEEE
Std.
488-1975, places
all
de-
vices
in
a
known quiescent
state.
System Controller— Monitors the
system controller switch.
Output Buffer
Full—
Used
as an
in-
terrupt to
the central
processor
while the output buffer of the
8292
is full.
The
feature
can be enabled
and disabled by the interrupt
mask
register.
Input Buffer
Not Full— Used
to
in-
terrupt
the central
processor while
the input buffer
of
the 8292
is
empty. This feature
is
enabled and
disabled by the interrupt
mask
register.
ATNO O
29
SRQ
21
REN
O
38
TCI
O
32
SPI
O
33
CLTH
O
27
IFCR
I
1
COUNT
I
39
X
1t
X
2
I
2,3
SYNC
11
V
CC
P.S.
40
V
ss
P.S. 7,20
Attention
Out—
Controls the
ATN
control line
of the
bus through
ex-
ternal
logic for tcs (take control
synchronously) purpose.
(ATN
is
a
GPIB
control
line,
as defined by
IEEE
Std. 488-1975.)
Service
Request— One
of
the
IEEE
control
lines.
Sampled by the 8292
when
it
is
controller in
charge,
if
true— SPI interrupt to
the
monitor
will
be generated.
The
Remote
Enable
bus
signal
selects
remote
or local
control of
the device
on
the bus.
A GPIB bus
management
line,
as defined by
IEEE
Std.
488-1975.
Task Complete
Interrupt—
Inter-
rupt to
the control
processor used
to
indicate that the task requested
was completed by the
8292 and
the
information
requested
is
ready
in
the
data
bus.
Special Interrupt—
Used as an
in-
terrupt
on events not
initiated
by
the central processor.
CLEAR LATCH
Output— Used
to
clear
the
IFCR
after
recognized by
the 8292. Usually
low (except
after
hardware Reset
),
will
be pulsed
low
when IFCR
is
recognized by
the 8292.
IFC Received (latched)—
The
8292
monitors the IFC Line
(when
not
system
controller)
through
this
pin.
Count Input—
When
enabled by
the
proper
command
the internal
counter
will
count external
events
through
this pin.
High
to
low
tran-
sition
will
increment the internal
counter by
one.
The
pin
is
sampled
once
per three internal
instruction
cycles
(7.5
/^sec
when
using 6
MHz
XTAL).
It
can be used
for
byte
counting
when
connected
to
NDAC
line,
or for
block counting
when
connected
to
the EOI
line.
Inputs for
a
crystal,
LC
or
an
ex-
ternal
timing signal to deter-
mine
the
internal oscillator
fre-
quency.
8041A
instruction
cycle syn-
chronization signal;
it
is
an
out-
put clock with a
frequency
of
XTAL-
15.
+ 5V
supply
input.
Circuit
ground
potential.
8-109
00741