Intel MCS48 User Manual page 266

8205
Logic Element Example
Probably
the
most
overlooked
application of the
8205
is
that of
a general
purpose
logic
element. Using the "on-chip"
enabling
gate, the
8205
can be configured
to gate
its
de-
coded
outputs with system timing
signals
and
generate
strobes that can be
directly connected
to
latches, flip-flops
and
one-shots
that are used
throughout the system.
An
excellent
example
of such an application
is
the
"state
decoder"
in
an
8008
CPU
based system.
The 8008
CPU
is-
sues three
bits of information
(SO, S1, S2) that indicate the
nature of the data on
the Data Bus
during each
machine
state.
Decoding
of these
signals
is
vital
to generate strobes
that can load the address
latches, control
bus
discipline
and
general machine
functions.
In
the
figure
below
a circuit
is
shown
using the
8205
as
the
"state
decoder"
for
an
8008 CPU
that
not only decodes
the
SO, S1,
S2
outputs but
gates these signals
with
the clock
(phase
2)
and
the
SYNC
output
of the
8008 CPU. TheTT
and
T2
decoded
strobes can connect
directly to devices like
8212s
for latching the address information. The
other
de-
coded
strobes
can be used
to generate
signals to control the
system data
bus,
memory
timing functions and
interrupt
structure.
RESET
is
connected
to the enable gate so that
strobes are not generated during system
reset,
eliminating
accidental loading.
The power
of such
a circuit
becomes
evident
when
a single
decoded
strobe
is
logically
broken down.
Consider
TT
out-
put,
the boolean equation
for
it
would
be:
fl
=
(S0-S1S2)(SYNC-Phase
2-Ftes7t)
A
six input
NAND
gate plus a few
inverters
would
be need-
ed
to
implement
this function.
The
seven remaining outputs
would
need
a similar circuit to duplicate
their function,
obviously
a substantial
savings
in
components
can be
achieved
when
using such
a
technique.
tf 2
^_y\_/^__n_/iv_A_v^_n__nL_n_^i^^
nc
rn_|r-T_
4
r-L_
f
pT_|p-u^
^-L^r-Uv—
\-4.
~w
SYSTEM RESET
Stata Control
Coding
s
s,
s
2
STATE
1
T1
1
1
Til
1
T2
WAIT
1
T3
1
1
1
1
,
STOP
T4
1 1
TS
7-28