Table of Contents
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iny
835578355-2**
16,384-BIT
ROM
WITH
I/O
'Directly
Compatible
with
8085A
CPU
"Directly
Compatible
with
8085A-2
2048
Words
x 8
Bits
Single
+
5V Power
Supply
Internal
Address
Latch
2 General
Purpose
8-Bit I/O
Ports
Each
I/O
Port Line Individually
Programmable
as
Input or
Output
Multiplexed
Address and
Data
Bus
40-Pin
DIP
The
Intel®
8355
is
a
ROM
and
I/O chip
to
be used
in
the
MCS-85™
microcomputer
system.
The
ROM
portion
is
organized as
2048 words by
8
bits.
It
has
a
maximum
access
time
of
400
ns
to
permit
use
with
no
wait states
in
the
8085A CPU.
The
I/O
portion
consists
of
2 general
purpose
I/O ports.
Each
I/O
port
has 8
port
lines,
and each
I/O
port
line
is
indivdu-
ally
programmable
as
input or output.
The
8355-2 has
a
300ns access
time
for
compatibility with the
8085A-2
microprocessor.
PIN
CONFIGURATION
BLOCK DIAGRAM
CE,C
CE
2
C
clkC
RESET
C
N.C.
(NOT
CONNECTED)
C
READY C
10/MC
ioSC
RDC
iowC
aleC
AD
C
AD,C
AD
2
C
AD
3
C
AD
4
C
AD
5
C
ad
6
c:
AD,C
v ssC
3v
cc
Dpb
7
>B
S
Hpb
s
Dpb
4
IlPBj
I)PB
2
Dpb,
3pb
Dpa
7
Dpa
6
3
pa,
Dpa
4
]pa
3
Dpa
2
Dpa,
Dpa
Da
10
Da
9
Da
8
-<=>
^
A
8~10(_
CE
2
-
CEi-
IO/M-
ALE-
RD-
iow-
RESET-
iOR-
2KX8
ROM
n
V
cc
(+5V)
V„
(OVI
INTEL
CORPORATION ASSUMES
NO
RESPONSIHtlTY
FOR
THE USE OF
ANY
CUCUTRY
OTHER THAN
CUCUTRY EMBODED
M
AN KTEl
PRODUCT.
NO
OTHER
CBCWT
PATENT
LICENSES
ARE
MPUED.
e
INTEL
CORPORATION, 1979
6-54
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