Intel MCS48 User Manual page 403

8041 A/8741
A
FEATURES
AND ENHANCEMENTS
UPI-41
UPI-41A
1.
Single
Data Bus
Buffer
NVwl
IVvAV
2.
4
Bits of
Status
1
1 1
UNDEFINED
Fl
F0 IBF
OBF
D
2
D!
3.
RD
and
WR
are
level triggered. IBF,
OBF,
Ft
and INT
change
internally
when RD
or
WR
are low.
\
FLAGS AFFECTED
/
4.
P
24
and P
2 5
are port pins
only.
1.
Two
Data
Bus
Buffers,
one
for
input
and one
for out-
put.
This allows a
much
cleaner Master/Slave
pro-
tocol.
D0-D7
INPUT
DATA
BUS
BUFFER
(8)
INTERNAL
DATA BUS
OUTPUT
DATA
BUS
BUFFER
(8) MV
2.
8 Bits of Status
ST
7
ST
6
ST5 ST
4
Fl
F
IBF
OBF
D
7
D
6
D
2
ST4-ST7
are
user definable status
bits.
These
bits are
defined by
the
"MOV
STS,
A"
single byte, single
cycle
instruction. Bits
4-7
of
the accumulator
are
moved
to bits
4-7
of
the status
register. Bits
0-3
of
the status register are not affected.
MOV
STS, A
Op
Code:
90H
10
°0
3.
RD
and
WR
are
edge
triggered. IBF,
OBF, F
:
and INT
change
internally after the
trailing
edge
of
RD
or
WR.
r
FLAGS AFFECTED
Y
V
P24
and P
2 5
are port pins or Buffer Flag pins which
can be used
to interrupt
a master
processor.
These
pins default
to port
pins on Reset.
If
the
"EN FLAGS"
instruction
has been executed,
P
24
becomes
the
OBF
(Output Buffer
Full) pin.
A
"1"
written to
P
24
enables
the
OBF
pin (the pin
outputs
the
OBF
Status
Bit).
A
"0"
written to
P
24
disables the
OBF
pin (the pin
remains
low).
This
pin
can be used
to
indicate that
valid
data
is
available
from
the UPI-
41A
(in
Output Data Bus
Buffer).
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