Intel MCS48 User Manual page 347

8259A
8259A
A.C.
CHARACTERISTICS
T
A
= 0*C
to
70X
V
cc
= 5V ±
5%
(8259A-8)
V
cc
=
5V ± 10%
(8259A)
TIMING
REQUIREMENTS
8259A-8 8259A
Symbol
Parameter
Mln. Max.
Mln.
Max.
Units
Test Conditions
TAHRL
AO/CS Setup
to
RD/iNTAi
50
ns
TRHAX
AO/CS Hold
after
RD/fNTAt
5
ns
TRLRH RD
Pulse Width
420
235
ns
TAHWL
A0/C"S
Setup
toWRi
50
ns
TWHAX
AO/CS Hold
after
WRt
20
ns
TWLWH WR
Pulse Width
400
290
ns
TDVWH
Data Setup
to
WRt
300
240
ns
TWHDX
Data Hold
after
WRt
40
ns
TJLJH
Interrupt
Request Width
(Low) 100
100
ns See Note
1
TCVIAL
Cascade
Setup
to
Second
or Third
INTA!
(Slave Only)
55
55
ns
TRHRL
End
of
RD
to
Next
Command
300 160
ns
TWHRL
End
of
WR
to
Next
Command
370
190 ns
Note:
1.
This
Is
the
low time
required
to clear
the
Input latch
m
the edge
triggered mode.
TIMING RESPONSES
8259A-8 8259A
Symbol
Parameter
Mln. Max.
Mln.
Max.
Units Test Conditions
TRLDV
Data
Valid
from RD/INTA4
300
200
ns
C
of
Data
Bus
TRHDZ
Data
Float after
RD/iNTAt
10
200
100 ns
Max.
test
C =
100
pF
TJHIH
Interrupt
Output Delay
400
350
ns
Min.
test
C=
15
pF
TIALCV
Cascade
Valid
from
First
INTAI
(Master Only)
565 565
ns
C
lNT
=100pF
Cenable = 15pF
TRLEL
Enable
Active
from
RDi
or
INTAi
160
125 ns
TRHEH
Enable
Inactive
from
RDt
or
INTAt
325
150 ns
TAHDV
Data
Valid
from
Stable Address
350 200 ns
TCVDV
Cascade
Valid to Valid
Data
300 300
ns
CAPACITANCE
T
A
=25*C;
V
cc
=
GNO
= 0V
Symbol
Parameter
Mln. Typ- Max.
Unit Test Conditions
Input Capacitance
10
pF fc=1
MHz
I/O
Capacitance
20
pF
Unmeasured
pins returned
to
V
ss
Input
and
Output
Waveforms
for
A.C. Tests
0.45
8-57