Intel MCS48 User Manual page 239

iny
2101A
256 X
4
BIT
STATIC
RAM
2101A-2 250 ns Max.
2101A
350 ns Max.
2101A-4 450 ns Max.
256
x 4
Organization
to
Meet Needs
for
Small
System Memories
Single
+5V Supply
Voltage
Directly
TTL
Compatible:
All
Inputs
and
Output
Statis
MOS: No
Clocks
or Refreshing
Required
Simple
Memory
Expansion: Chip Enable
Input
Inputs Protected:
All
Inputs
Have
Pro-
tection
Against
Static
Charge
Low
Cost Packaging: 22
Pin
Plastic
Dual
In-Line Configuration
Low
Power:
Typically
150
mW
Three-State Output: OR-Tie
Capability
Output
Disable Provided
for
Ease
of
Use
in
Common
Data Bus Systems
The
Intel®
2101
A
is
a
256
word
by
4-bit static
random
access
memory
element
using N-channel
MOS
devices integrated on
a
monolithic
array.
It
uses
fully
DC
stable
(static) circuitry
and
therefore requires
no
clocks or
refreshing
to operate.
The
data
is
read out nondestructively
and
has
the
same
polarity
as the input
data.
The
21 01
A
is
designed
for
memory
applications
where
high
performance, low
cost,
large
bit
storage,
and
simple
interfacing are
important design
objectives.
It is
directly
TTL
compatible
in
all
respects: inputs, outputs,
and
a
single
+5V
supply.
Two
chip-enables allow easy
selection of
an
individual
package
when
outputs are OR-tied.
An
output
disable
is
provided so
that data inputs
and
outputs can be
tied for
common
I/O systems.
The
output
disable function eliminates the
need
for bi-directional logic
in
a
common
I/O system.
The
Intel®
2101A
is
fabricated with N-channel
silicon
gate technology. This technology
allows the design and production
of
high performance, easy-to-use
MOS
circuits
and
provides
a
higher functional density on
a monolithic chip than
either
conventional
MOS
technology
or
P-channel
silicon
gate technology.
Intel's
silicon gate
technology
also
provides
excellent protection against contamination. This permits the use
of low cost
plastic
packaging
PIN
CONFIGURATION
LOGIC
SYMBOL
Ao
A
1
DO,
A
2
A
3
D0
2
A
4
A
5
D0
3
A
6
A
7
D0
4
Dl,
Dl
?
OD
Dl
3
Dl
4
WE CE2
CE1
Y
I
T
PIN
NAMES
DI,-DI
4
A„-A
7
DATA
INPUT
CE
2
CHIP
ENABLE
2
ADDRESS
INPUTS OD OUTPUT
DISABLE
WE WRITE ENABLE
DO,-D0
4
DATA OUTPUT
CE,
CHIP ENABLE
1
V
cc
POWER
(+5V)
BLOCK DIAGRAM
IHTEL
CORPORATION ASSUMES NO
RESPONSIBILITY FOR THE USE
Of
ANY
CIRCUITRY OTHER THAN CIRCUITRY EMBODIED
IN
AN
INTEL PRODUCT. NO OTHER
CIRCUIT PATENT LICENSES ARE
IMPLIED
©
INTEL CORPORATION, 1979
7-1