Intel MCS48 User Manual page 353

8278
PIN
DESCRIPTION
The 8278
is
packaged
in
a 40-pin DIP.
The
following
is
a
brief
functional description of
each
pin.
Signal
Pin
No.
Description
D0-D7
12-19 Three-state, bi-directional
data
bus
lines
used
to transfer
data
and
com-
mands between
the
CPU
and
the
8278.
WR
10 Write strobe
which enables
the
mas-
ter
CPU
to write
data
and
com-
mands between
the
CPU
and the
8278.
RD
8
Read
strobe
which enables the
mas-
ter
CPU
to
read data
and
status
from
the
8278
internal registers.
CS
6
Chip
select input
used
to
enable
reading
and
writing to
the 8278.
Ao
9
Address
input
used by
the
CPU
to
indicate control or data.
RESET
4
A
low signal
on
this
pin resets the
8278.
X-i,
X2
2,3
Inputs for crystal,
L-C or external
timing signal to
determine
internal
oscillator
frequency.
IRQ 23
Interrupt
Request Output
to
the
master
CPU.
In
the
keyboard
mode
the
IRQ
line
goes low with
each
FIFO
read
and
returns high
if
there
is still
information
in
the
FIFO
or
an
ERROR
has
occurred.
M0-M6
27-33 Matrix scan
outputs.
These
out-
puts control a
decoder which scans
the
key
matrix
columns and
the 16
display
digits. Also,
the Matrix
scan
outputs are used
to
multiplex the
return lines
from
the
key
matrix.
RL
1
Input
from
the multiplexer
which
in-
dicates
whether
the key currently
being
scanned
is
closed.
HYS
22 Hysteresis output
to
the
analog
de-
tector. (Capacitive
keyboard config-
uration).
A "0"
means
the
key
cur-
rently
being
scanned has
already
been
recorded.
KCL
34
Key
clock output
to the
analog de-
tector (capacitive
keyboard
config-
uration)
used
to reset
the detector
before scanning
a key.
SYNC
11
High frequency
(400
KHz) output
signal used
in
the
key scan
to
detect
a closed key
(capacitive
keyboard
configuration).
B0-B3
35-38 These
four
lines
contain binary
coded
decimal display information
synchronized
to
the
keyboard
col-
umn
scan.
The
outputs are
for
multiplexed
digital
displays.
Signal Pin
No. Description
ERROR
24
Error signal.
This
line
is
high
when-
ever
two new
key closures are de-
tected during a single
scan
or
when
too
many
characters are entered
into
the
keyboard
FIFO.
It
is
reset
by
a
system
RESET
pulse or
by
a
"1"
input
on
the
CLR
pin or by the
CLEAR ERROR
command.
CLR
39
Input
used
to clear
an
ERROR
con-
dition
in
the 8278.
BP
21
Tone
enable
output.
This
line
is
high
for
10ms
following a
valid
key
closure;
it
is
set
high
and remains
high during an
ERROR
condition.
Vcc,
Vdd
40,26
+5
volt
power
input:
+5V ±
10%.
GND
20,7
Signal ground.
PRINCIPLES
OF OPERATION
The
following
is
a description of
the major elements
of
the
Programmable Keyboard/Display
interface device.
Refer
to
the block diagram
in
Figure
1.
I/O
Control
and
Data Buffers
The
I/O control section uses the
CS", Ao,
RD, and
WR
lines
to control data flow
to
and from the various internal
registers
and
buffers (see
Table
1).
All
data flow to
and
from
the
8278
is
enabled by CS.
The
8-bits of
information
being transferred
by
the
CPU
is
identified
by
Ao.
A
logic
one means
information
is
command
or statu
s.
A
logic
zero
means
the information
is
data.
RD
and
WR
determine the
direction of
data flow
through
the Data
Bus Buffer (DBB).
The
DBB
register
is
a bi-directional 8-bit
buffer register
which connects
the internal
8278 bus buffer registerto the
external bus.
When
the chip
is
not selected
(CS"
=
1)
the
DBB
is
in
the high
impedance
state.
The
DBB
acts as
an
input
when
(RD,
WR,
CS)
=
(1,0, 0)
and an output
when
(RD,
WR,
CS)
=
(0,1,
0).
CS Ao
WR
RD
Condition
1
Read
DBB
Data
1 1
Read
STATUS
1
Write
Data
to
DBB
1 1
Write
Command
to
DBB
1
X X X
Disable
8278 Bus
is
High Impedance
Scan Counter
The scan counter
provides the timing
to
scan
the
keyboard and
display.
The
four
MSB's
(M3-M6) scan
the
display
digits
and
provide
column
scan
to
the keyboard
via
a 4
to
16 decoder.
The
three LSB's (M0-M2)
are
used
to
multiplex the
row
return lines into the 8278.
8-63
00227A