Intel MCS48 User Manual page 246

2111A
FAMILY
2111A
(350 ns
ACCESS
TIME)
A.C.
CHARACTERISTICS
READ CYCLE
T
A
=
0°C
to
70°C,
V
cc
=
5V
±5%,
unless otherwise
specified.
Symbol
Parameter Min.
T
[1)
Typ. Max.
Unit Test Conditions
l
RC
Read Cycle 350
ns
tA
Access
Time 350
ns
t
r
,
t
f
=
20ns
tCO
Chip Enable To
Output 240
ns
Input Levels
=
0.8V
or
2.0V
tfJD
Output
Disable
To
Output 180
ns
Timing
Reference = 1.5V
t
DF
[2l Data
Output
to
High
Z
State 150
ns
Load
=
1
TTL
Gate
tQH
Previous
Read
Data Valid
after
change of Address
40
ns
and
C
L
-
100pF.
WRITE CYCLE
Symbol
Parameter Min.
Typ. Max.
Unit Test Conditions
%c
Write Cycle 220 ns
tAW Write
Delay
20 ns
t
r
,
t
f
- 20ns
tew
Chip Enable To
Write
200
ns
Input
Levels
=
0.8V
or
2.0V
tDW
Data Setup 200
ns
Timing
Reference - 1.5V
Load
-
1
TTL
Gate
and
C
L
=
100pF.
l
DH
Data Hold
ns
t
W
P
Write Pulse
200
ns
tWR Write
Recovery
ns
t
DS
Output
Disable
Setup 20 ns
2111A-4
(450 ns
ACCESS
TIME)
A.C.
CHARACTERISTICS
READ
CYCLE
T A
=
0°C
to 70°C,
V C c = 5V
±5%,
unless
otherwise
specified.
Symbol
Parameter Min. Typ. Max.
Unit Test Conditions
t
RC
Read
Cycle
450
ns
tA
Access
Time 450
ns
t
r
,
t
f
=
20ns
tco
Chip Enable
To Output 310
ns
Input Levels
=
0.8V
or
2.0V
tOD
Output
Disable
To Output 250
ns
Timing Reference
-
1.5V
tDF
I
2
'
Data
Output
to
High Z
State 200 ns
Load
-
1
TTL
Gate
and
C
L
=
100pF.
tQH
Previous
Read Data
Valid
after
change
of
Address
40 ns
WRITE CYCLE
Symbol
Parameter Min.
Typ. Max. Unit
Test
Conditions
twe Write Cycle 270
ns
tAW
Write Delay 20
ns
t
r
,
tf
-
20ns
tew
Chip Enable
To
Write 250
ns
Input
Levels
=
0.8V
or
2.0V
tow
Data Setup 250
ns
Timing
Reference
-
1.5V
Load
=
1
TTL
Gate
and
C
L
=
100pF.
*DH
Data Hold
ns
t
W
P
Write Pulse
250
ns
twR Write Recovery
ns
t
DS
Output
Disable Setup
20
ns
NOTES:
1
.
Typical values are for
T A
= 25°C and nominal supply voltage.
2.
tQF
is
witn
respect to the trailing
edge of CEi
,
CE2,
or
OD, whichever occurs
first.
7-8