Intel MCS48 User Manual page 331

intel
8259A
PROGRAMMABLE
INTERRUPT
CONTROLLER
MCS-86™
Compatible
MCS-80/85™ Compatible
Eight-Level
Priority
Controller
Expandable
to
64
Levels
Programmable
Interrupt
Modes
Individual
Request
Mask
Capability
Single
+ 5V
Supply (No
Clocks)
28-Pin Dual-ln-Line
Package
The
Intel®
8259A Programmable
Interrupt Controller
handles up
to
eight vectored
priority
interrupts for the
CPU.
It
is
cascadable
for
up
to
64 vectored
priority interrupts
without
additional
circuitry.
It
is
packaged
in
a
28-pin DIP, uses
NMOS
technology and
requires a single
+5V
supply.
Circuitry
is static,
requiring
no
clock
input.
The 8259A
is
designed
to
minimize
the software
and
real
time overhead
in
handling
multi-level priority interrupts.
It
has
several
modes,
permitting optimization
for a variety of
system
requirements.
The 8259A
is
fully
upward
compatible with the
Intel® 8259.
Software
originally written
for
the 8259
will
operate
the
8259A
in
all
8259 equivalent
modes
(MCS-80/85, Non-Buffered, Edge
Triggered).
PIN
CONFIGURATION BLOCK DIAGRAM
csC
wrC
rdC
D,C
CASOC
CAS1
C
gndC
1
^"^
28
=w
cc
2
27
3\
3
26
Uinta
4
25
DlR7
5 24
UIR6
6 23
DlR5
7
22
8259A
8 21
UlR4
DlR3
9 20
3
IR2
10 19
UlRI
11 18
UlRO
12
17
J INT
13
16
D
SP/EN
14 15
13
CAS
2
PIN
NAMES
D
7
D
o
DATA
BUS
(Bl
DIRECTIONAL)
RD READ
INPUT
WR
WRITE INPUT
\
COMMAND
SELECT ADDRESS
cs CHIP SELECT
CAS2 CASO
CASCADE
LINES
SP/EN
SLAVE
PROGRAM
INPUT/ENABLE
INT
INTERRUPT OUTPUT
INTA
INTERRUPT ACKNOWLEDGE
INPUT
IR0-IR7
INTERRUPT REQUEST
INPUTS
READ/
WRITE
LOGIC
CASO
CAS1
CAS
2
CASCADE
BUFFER/
COMPARATOR
INT
f
CONTROL
LOGIC
SERVICE
REG
IISRI
c:
INTERRUPT
REQUEST
REG
IIRR)
-IR2
-IR3
-IR4
-IRS
-IR6
I
-N
INTERRUPT
MASK REG
IIMR)
INTERNAL BUS
^fcOWOMTIMuJra
N °
RESP0NSIBIUTY f0R
M
USE 0F
"
NY
CIRCUITRV 0TH£R THAN
CIRCUITRY EMB00IED
IN
AN
1NTEL
ra "0"CT. NO
OTHER
CIRCUIT PATENT LICENSES
ARE IMPLIED.
8-41