Intel MCS48 User Manual page 130

APPLICATION EXAMPLES
OPTIONAL GATE
TO PREVENT
"HOLE"
IN
GND
PROGRAM
MEMORY
40
{26 {20
Vcc
Vdq
Vss
XTAL1
8049
8048
8748
pio
P11
P12
P13
P14
P15
P16
P17
P20
P21
P22
P23
P24
P25
P26
P27
DBO
DB1
DB2
DB3
DB4
DB5
DB6
DB7
ALE
PSEN
PROG WR RD
x>
CAN BE SUPPLIED
BY SYSTEM
.
RESET
OR PORT
LINE
OF
8048
+5V +5V
GND GND
40
5 20
1
A8
A9
A10
ADO
AD1
AD2
AD3
AD4
AD5
AD6
AD7
IOR
IOW
RD
ALE
CE
RESET
Vcc
v
D d
Vss ce
8355
8755A
2Kx8
ROM
7 3 6
r
NC NC
GND
20
v
C
c
Vss
ADO
AD1
AD2
AD3
AD4
AD5
AD6
AD7
8156
256
x 8
RAM
RESET TIMER
OUT
PAO
PA1
PA2
PA3
PA4
PA5
PA6
PA7
PBO
PB1
PB2
PB3
PB4
PB5
PB6
PB7
PAO
PA1
PA2
PA3
PA4
PA5
PA6
PA7
PCO
PC1
PC2
PC3
PC4
PC5
PBO
PB1
PB2
PB3
PB4
PB5
PB6
PB7
I/O
• This configuration
is
explained
in
section 3.4
THE THREE
CHIP
SYSTEM
5-10