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iny
2708
8K
AND
4K
UV ERASABLE
PROM
Max.
Power
Max.
Access
Organization
2708
800
mW
450 ns
1Kx8
2708L
425
mW
450 ns
1Kx8
2708-1
800
mW
350 ns
1Kx8
2704
800
mW
450 ns
512x8
Low
Power
Dissipation
—
425
mW
Max.
(2708L)
Fast
Access Time
—
350 ns Max.
(2708-1)
Static
—
No
Clocks Required
Data
Inputs
and Outputs
TTL
Compatible
during both
Read and
Program
Modes
Three-State
Outputs
—
OR-Tie
Capability
The
Intel"
2708
is
a
8192-bit
ultraviolet
light
erasable
and
electrically
reprogrammable
EPROM,
ideally
suited
where
fast
turnaround
and
pattern
experimentation
are
important requirements.
All
data inputs
and
outputs
are
TTL com-
patible
during both the read
and program modes. The
outputs
are
three-state,
allowing
direct interface
with
common
system bus
structures.
The 2708L
at
425
mW
is
available
for
systems
requiring
lower
power
dissipation
than from the 2708.
A
power
dissipation
savings
of
over
50%,
without
any
sacrifice
in
speed,
is
obtained
with the 2708L.
The 2708L
has
high
input
noise
immunity and
is
specified
at
10%
power
supply
tolerance.
A
high-speed
2708-1
is
also available
at
350 ns
for
microprocessors
requiring
fast
access
times.
For smaller
size
systems
there
is
the
4096-bit
2704 which
is
organized as
512 words by
8
bits. All
these devices have the
same
programming and
erasing specifications
of
the 2708.
The
2704
electrical
specifications are the
same
as
the 2708.
The
2708
family
is
fabricated with the
N-channel
silicon
gate
FAMOS
technology and
is
available
in
a
24-pin dual
in-line
package.
PI
IM
CONFIGURATION
BLOCK
DIAGRAM
A
?
C
1
A([!
As[3
A
4
C
4
A
3
C
5
A*C
6
AiQ
7
(LSB)
AoC
8
(LSB)
Oo
C
9
Old
10
O?
C
11
'*sC
12
3*>
3
A
9
'
1
'
[]cS/WE
3*00
3
PROGRAM
3
°7
(MSB!
3
°6
Ho
5
3
04
D03
DATA OUTPUT
O0-O7
I
NOTE
1:
PIN 22
MUST
BE
CONNECTED
TO
VSS
FOR THE
2704.
PIN
NAMES
cs/vv
CHIP
SELECT
LOGIC
OUTPUT BUFFERS
>
—
*
DECODER
v
GATING
A
3
X
DECODER
64
X
128
ROM ARRAY
INPUTS
A
6
T
A
7
A
A0-A9
ADDRESS
INPUTS
Oi-0»
DATA
OUTPUTS/INPUTS
C5/WE
CHIP
SELECT/WRITE
ENABLE
INPUT
PIN
CONNECTION DURING READ OR
PROGRAM
PIN
NUMBER
1
ADDRESS
1
DATA
I/O
INPUTS
9
11,
18.
V
Ss
PROGRAM
v
D0
CS/WE
v
BB
Vcc
MODE
13
17
22.
23
12
18
19
20
21
24
I
READ
Dout
Ain
GND
GND
+12
VlL
-5
+5
DESELECT
HIGH IMPEDANCE
DON'T
CARE
GND
GND
+12
V|H
-5
+5
1
PROGRAM
i
Din
Ain
GND
1
1
PULSED
26V
+12
V|HW
-5
+5
SlStttcoSoSJnwwra
"°
RESroHSBIllTY
m m
"*
"
m
C
"
CU,TR,
'
OTHER
™*
N
CRCUITRV
lmxm
m
AN
INTEL
PR0DUCT
'
n°
oiher
ci
« cu|
t
p«ent
licenses
are
implied.
7-13
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