Intel MCS48 User Manual page 49

SINGLE
COMPONENT
SYSTEM
SINGLE STEP CIRCUIT
SINGLE
5IOK
STEP
MOMENTARY
PUSHBUTTON
Jl
On
> CLOCK
<]
SINGLE STEP TIMING
ALE
/
h—
/
-<
—
cc
—
ii—
X
SS
-<
-^
/
^\
PCO-7
N
—
??-
PCO-7
>-
P20 23
I/O
"
X
PC8-11
Y
ACTIVE CYCLE
I/O
v
w
_v\
e?
_
STOP CYCLE
PC8
11
x_
STOP CYCLE
|
2.1.14
Power
Down Mode
(8048, 8049, 8039,
8035L)
Extra
circuitry
has been added
to
the
8048
ROM
version
to
allow
power
to
be removed
from
all
but the
64/128
x 8 data
RAM
array
for
low
power standby
operation.
In
the
power
down mode
the contents
of
data
RAM
can be maintained
while
drawing
typically
10%
to
15%
of
normal
operating
power
requirements.
Vcc serves as
the
5V
supply
pin for
the bulk
of
8048
circuitry
while the
Vdd
pin supplies
only the
RAM
array.
In
normal
operation both
pins are
at
5V
while
in
standby
Vcc
is
at
ground and
only
Vqd
is
maintained
at 5V.
App
lying
R
eset to the
processor through
the
RESET
pin inhibits
any
access
to the
RAM
by the processor
and
guarantees
that
RAM
cannot be
inadvertently altered as
power
is
removed from Vcc-
2-13