Intel MCS48 User Manual page 259

iny
5101
FAMILY
256 x 4 BIT
STATIC
CMOS RAM
P/N
Typ. Current
@
2V
(MA)
Typ. Current
@
5V
(MA)
Max Access
(ns)
5101L
0.14
0.2
650
5101L-1
0.14
0.2
450
5101L-3
0.70 1.0
650
Single
+5V Power Supply
Ideal for Battery
Operation
(5101
L)
Directly
TTL
Compatible:
All
Inputs
and
Outputs
Three-State
Output
The
Intel® 5101
is
an
ultra-low
power
1024-bit (256
words
X
4
bits)
static
RAM
fabricated
with an advanced
ion-implanted
silicon
gate
CMOS
technology.
The
device has
two
chip enable
inputs.
Minimum
standby current
is
drawn by
this device
when
CE2
is
at a
low
level.
When
deselected the
5101 draws from
the
single 5-volt
supply only 10 microamps.
This device
is
ideally
suited for
low power
applications where battery operation or battery backup
for non-volatility are required.
The
5101
uses fully
DC
stable
(static)
circuitry;
it is
not
necessary to pulse
chip
select for
each address
transition.
The
data
is
read
out
non-destructively
and
has the
same
polarity as
the input
data. All
inputs
and
outputs
are directly
TTL
compatible.
The
5101
has separate data input and
data
output
terminals.
An
output
disable function
is
provided
so that the data inputs
and
outputs
may
be wire
OR-ed
for use
in
common
data I/O systems.
The 5101
L has
the additional feature
of guaranteed
data retention at a
power
supply
voltage as
low
as
2.0
volts.
A
pin
compatible N-channel
static
RAM,
the Intel®
2101 A,
is
also available for
low
cost applications
where
a
256 X
4
organiza-
tion
is
needed.
The
Intel
ion-implanted,
silicon gate,
Complementary
MOS
(CMOS)
process allows the design and production
of ultra-low
power,
high
performance memories.
PIN
CONFIGURATION
*
3
CZ
1
A
2
[Z
A,
*0
As
A
6
GND
QZ
LOGIC
SYMBOL
ZKc
21
Z]
A
4
20
fU
R/W
ceT
OD
CE2
16
M
DO,
15
ZD
Dl„
14
IlDOj
-
13
Z2
Dl
3
12
Z2
D
°
2
TRUTH TABLE
Ao
A,
A
7
A
3
A
a
A
5
A
6
A
7
Dl,
DO
Dl
?
DO
Dl,
DO
Dl
4
DO
OD
R/W
CE2 CE1
mr
CE, CE
2
OD
R/W
Din
Output
Mode
H
X
X X X HighZ
Not
Selected
X
L
X X X
HighZ Not
Selected
X X H H X
HighZ
Output Disabled
L
H H
L
X
HighZ
Write
L
H
L
L
X
OlN Write
L
H
L
H X
Dqut Read
BLOCK DIAGRAM
CELL
ARRAY
32
ROWS
32
COLUMNS
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SELECT
BUFFERS
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A
5
A
6
A
7
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NUMBERS
Wia
CORPORATION ASSUMES
NO
RESPONSBHITV FOR
THE USE OF ANY
CIRCUITRY
OTHER THAN
CIRCUITRY
e
INTEL CORPORATION, 1979
EMBODIED
IN
AN
INTEL
PRODUCT. NO OTHER
CIRCUIT PATENT
LICENSES ARE
IMPLIED.
7-21