Intel MCS48 User Manual page 345

Intl.
•
Mnemonic
8259A
SUMMARY OF
8259A
INSTRUCTION SET
(Cont.)
AO 07
M
D5 D4 03 02
01
DO
Operation Description
62
0CW3
RR
1
Read request
register
63
0CW3 SM
1 1
Set special
mask mode
64
0CW3 RSM
1
Reset
special
mask mode
Note:
1.
In
the master
mode SP
pin
=
1,
in
slave
mode SP
=
Cascading
The 8259A can be
easily interconnected
in
a
system
of
one master with up
to eight slaves to
handle up
to
64
priority levels.
A
typical
MCS-80/85 system
is
shown
in
Figure
2.
The
master
controls,
through
the 3
line
cascade
bus,
which
one
of
the
slaves
will
release the corresponding
address.
As shown
in
Figure
2,
the slave
interrupt
outputs
are
connected
to
the
master
interrupt
request
inputs.
When
a slave request
line is
activated
and afterwards acknowl-
edged, the master
will
enable
the
corresponding
slave
to release the
device routine address during bytes
2
and
3
of
INTA.
(
Byte 2 only
for
MCS-86
>.
The IRO
input
should
not
be connected
to
a slave
8259A
unless IR1-IR7
also
have slaves attached.
The cascade bus
lines are
normally low
and
will
contain
the
s lave
address code from
the
trailing
edge
of
the
first
INTA
pulse to the
trailing
edge
of
the third pulse.
It
is
obvious
that
each 8259A
in
the
system must
follow a
separate
initialization
sequence and can
be
pro-
grammed
to
work
in
a different
mode.
An
EOI
command
must
be issued
twice:
once
for
the
master and once
for
the
corresponding
slave.
An
address decoder
is
required
to activate
the
Chip
Select (CS)
input of
each
8259A.
The cascade
lines of the
Master
8259A
are activated for
any
interrupt input,
even
if
no
slave
is
connected
to that
input.
ADDRESS
BUS
1
161
CONTROL
BUS
DATA BUS
III
7^
iz
izJ
7S
<>
\>r
CS
A, INT
CASO
6259A
CAS
,
SLAVE A
CAS
2
SPIEN7 6
S
4
3 2
10
9
f
i i
i
t
! !
T
7 C 5 4 3 2
1
A
t
7S
iz
iz
CS A,
INT
CASO
82S9A
SLAVES
CAS
2
SP/EN?
6 5
4
3 2
10
T
f t t
T
t t
7 6 5 4 3 2
10
CS A„
CASO
8259A
MASTER
CAS
2
SPIENM7 M6
MS
M4
M3M2
Ml MO
<? i
1
i i t
i.
»
1
3 2
10
Figure
2.
Cascading
the
8259A
INTERRUPT REQUESTS
8-55