Intel MCS48 User Manual page 312

8255A/8255A-5
(RESET)
Reset.
A
"high on
this input clears the control register
and
all
ports
(A,
C, C) are set
to
the input
mode.
Group
A
and Group B
Controls
The
functional configuration
of
each
port
is
program-
med
by the
systems
software.
In
essence,
the
CPU
"out-
puts" a control word
to the 8255A.
The
control
word
con-
tains
information such
as "mode",
"bit set", "bit reset",
etc.,
that
initializes
the functional configuration
of
the
8255.
Each
of the Control blocks (Group
A
and
Group
B)
accepts
"commands"
from
the Read/Write Control
Logic, receives
"control
words" from
the internal data bus and
issues
the
proper
commands
to
its
associated
ports.
Control
Group
A -
Port
A
and Port
C
upper (C7-C4)
Control
Group
B
-
Port
B and
Port
C
lower (C3-C0)
The
Control
Word
Register
can Only
be written
into.
No
Read operation
of the Control
Word
Register
is
allowed.
Ports A,
B,
and
C
The 8255A
contains
three
8-bit
ports
(A,
B,
and
C). All
can be configured
in
a
wide
variety of
functional charac-
teristics
by the
system
software
but
each has
its
own
special features or "personality" to further
enhance
the
power and
flexibility of
the 8255A.
Port A.
One
8-bit
data output
latch/buffer
and one
8-bit
data input
latch.
Port
B.
One
8-bit
data input/output
latch/buffer
and one
8-bit
data input
buffer.
Port C.
One
8-bit
data output
latch/buffer
and one
8-bit
data input buffer (no
latch for input).
This
port
can be
divided into
two
4-bit
ports
under
the
mode
control.
Each
4-bit
port contains a
4-bit
latch
and
it
can be used
for the control signal outputs
and
status signal inputs
in
conjunction with
ports
A
and
B.
PIN
CONFIGURATION
11-OlRCCTKWAt DATA 8US
•".<C=3
:
DATA
SUFFER
c
KES8I -
REAO'
•miff
COWTROl
tOOIC
C
c=>
™
t=$
c=c>
«&
c
1
N
"Vj
lOvveb
|>r
I
c=o
c
Figure
2.
8225A
Block Diagram
Showing Group
A
and
Group B
Control Functions
PA3C
1
W
40
Z]
PA4
PA2 £
39
Z\
PA5
PA1
Q
3 38
J
PA6
PAOC
4 37 ^}
PA7
55
Q 5 36
Z\
wS
cs
C 6
35
j
RESET
gndC
7
34
>.
AlC
8
33
^D,
AO
C 9
32
D»!
PC7Q
PC6C
10
11
825SA
31
30
bo
3
Do.
l>C5 C. 12 29
Do
s
PC4C
13
28
>.
PCoT
14
"Jo,
pci
{Z
15
Sb
nv
cr
PC2 C
16
25
-
;
pb;
PC3
rj
17 24
J
PB6
PBOQ
18 23
~3 PB5
PB1
[^
19
22 31
PB4
PB2Q
20 21 31 p
B3
PIN
NAMES
tECTIONALI
D,
D„
DATA
BUS
(81
OIF
RESET
RESET INPUT
CS
'
RD
CHIP
SELECT
READ
INPU'T
SS
WR
'""
ao/aT'
~
WRITE
INPUT
PORT ADDRE
PORT
ATBTf)"
PA7PA0
PB7PB0
PORTB
(BITI
PC7-PC0
PORTC
(BITI
I
v
Cc
5
VOLTS
,
GND
9
VOLTS
8-22