Intel MCS48 User Manual page 349

iny
8273
PROGRAMMABLE
HDLC/SDLC
PROTOCOL
CONTROLLER
Programmable NRZI Encode/Decode
N-Bit
Reception
Capability
HDLC/SDLC
Compatible
Frame
Level
Commands
Full
Duplex, Half Duplex, or
Loop
SDLC
Operation
Up
to
64K Baud
Transfers
Two
User Programmable
Modem
Control Ports
Automatic
FCS
(CRC) Generation and
Checking
Digital
Phase Locked Loop Clock
Recovery
Minimum
CPU
Overhead
Fully
Compatible
with 8080/8085
CPUs
Single
+
5V
Supply
40-Pin
Package
The
Intel®
8273 Programmable
HDLC/SDLC
Protocol Controller
is
a dedicated device designed
to
support the
ISO/C-
CITT's
HDLC
and IBM's
SDLC
communication
line
protocols.
It
is
fully
compatible
with
Intel's
new
high
performance
microcomputer systems such
as
the
MCS-85™.
A
frame
level
command
set
is
achieved by a unique microprogrammed
dual processor chip architecture.
The
processing
capability
supported by the
8273
relieves
the
system
CPU
of
the low
level
real-time
tasks normally associated with
controllers.
PIN
CONFIGURATION BLOCK DIAGRAM
FLAG DET L
"
40
3 v
cc
Tx INT £
2
39 3
PB
4
CLK C
3 38 2
^
RESET
C 4 37
i*i
TxDACK C
5 36 3 PB7
TxDRQ C
6 35
3 RTS
RxDACK C
7 34 2
pa7
RxDRQ C
8 33 2
PA^
So C
9 32 3 PA,
WR C
10
8273 31
3
CD
Rx INT C
"
30 3
5TS
DBO C
12
29
3
TxD
OB1 C 13
28 2
TxC
DB2 C 14
27 2
RxC
DB3
C
15
26 3
RxD
DB4
C
16 25 3
32xCLK
DB5
C
17 24 3 CS
DB6
fj
18
23
1
OPLL
DB7
£
19 22 3
Al
GND £
20
21 3
\
PIN
NAMES
DBO-DB7
FLAG DET
TxINT
CLK
RESET
Tx
DACK
TxDRQ
RB
Bfi
Rx
DACK
RxDRQ
RxINT
A0-A
1
BFCl
DATA
BUS
(8
BITS)
FLAG DETECT
TRANSMITTER INTERRUPT
CLOCK
INPUT
RESET
TRANSMITTER DMA ACKNOWLEDGE
TRANSMITTER
DMA
REQUEST
REAO
INPUT
WRITE
INPUT
RECEIVER
DMA
ACKNOWLEDGE
RECEIVER
DMA
REQUEST
RECEIVER INTERRUPT
COMMANO
REGISTER SELECT
ADDRESS
DIGITAL PHASE LOCKED LOOP
RxC
TxC
TxD
CTS
RTS
CHIP SELECT
32
TIMES CLOCK
RECEIVER
DATA
RECEIVER CLOCK
TRANSMITTER CLOCK
TRANSMITTER
DATA
CLEAR TO SEND
CARRIER DETECT
GP INPUT
PORTS
GP OUTPUT PORTS
REQUEST TO SEND
+5
VOLT
SUPPLY
GROUND
REGISTERS
TxINT RESULT
COMMAND
RxINT RESULT
PARAMETER
TEST
MODE
STATUS
RESULT
o
-o
DATA
BUS
BUFFER
o
TxDRQ »-
TxDACK
—
RxDRQ »-
RxDACK
—
TxINT
—
RxINT
—
READ/
WRITE
DMA/
CONTROL
LOGIC
IT
INTERNAL DATA
BUS
CPU INTERFACE
w
o
TxD
TxC
o
RxD
RxC
MODEM
INTERFACE
S^o
?^!^™
8
!!?.
5 "°
RESP0NSBILITY
™
THE USE OF ANY CBCWTRY
OTHER THAN
CBCWTRY
EMBODIED
IN
AN
INTEL PRODUCT. NO
OTHER CIRCUIT PATENT
LICENSES ARE
IMPLIED.
C
INTEL CORPORATION, 1979
8-59
00743A