Intel MCS48 User Manual page 318

8255A/8255A-5
Input Control Signal Definition
STB
(Strobe
Input).
A
"low" on
this input
loads data
into
the input
latch.
IBF
(Input Buffer
Full F/F)
A
"high" on
this
output
indicates that
the data has
been
loaded
into
the input
latch;
in
essence, an
acknowledgement
IBF
is
set
by
STB
input being
low and
is
reset
by
the
rising
edge of the
RD
input.
INTR
(Interrupt
Request)
A
"high" on
this
output can
be used to interrupt the
CPU
when
an input
device
is
requesting service.
INTR
is
set
by
the
STB
is
a
"one", IBF
is
a
"one" and
INTE
is
a
"one".
It is
reset
by
the
falling
edge
of
RD.
This procedure allows
an input device to request
service
from
the
CPU
by
simply
strobing
its
data
into
the
port.
INTE
A
Controlled
by
bit set/reset
of
PC
4 .
INTEB
Controlled
by
bit set/reset of
PC
2
.
MODE
1
(PORT
A)
CONTROL
WORD
MODE
1
(PORT
B)
CONTROL
WORD
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
RD «-0
PB
7
-PB
<^
1
INTE
1
1
B
1
PC
2
STB
B
r-
J
Q.
PC,
"
[BF B
INTRb
Figure
6.
MODE
1
Input
Figure
7.
MODE
1
(Strobed Input)
8-28
00744A