Appendix B Pipeline And Execution Unit Resources Overview; Fetch And Decode Pipeline Stages - AMD Athlon Processor x86 Optimization Manual

22007E/0—November 1999

Fetch and Decode Pipeline Stages

Fetch and Decode Pipeline Stages
Pipeline and Execution Unit
Resources Overview
The AMD Athlon™ processor contains two independent
execution pipelines — one for integer operations and one for
floating-point operations. The integer pipeline manages x86
integer operations and the floating-point pipeline manages all
x87, 3DNow!™ and MMX™ instructions. This appendix
describes the operation and functionality of these pipelines.
Figure 5 on page 142 and Figure 6 on page 142 show the
AMD Athlon processor instruction fetch and decoding pipeline
stages. The pipeline consists of one cycle for instruction fetches
and four cycles of instruction alignment and decoding. The
three ports in stage 5 provide a maximum bandwidth of three
MacroOPs per cycle for dispatching to the instruction control
unit (ICU).
AMD Athlon™ Processor x86 Code Optimization
Appendix B
141