AMD Athlon Processor x86 Optimization Manual page 230

AMD Athlon™ Processor x86 Code Optimization
Table 22. Floating-Point Instructions (Continued)
Instruction Mnemonic
FIADD [mem32int]
FIADD [mem16int]
FICOM [mem32int]
FICOM [mem16int]
FICOMP [mem32int]
FICOMP [mem16int]
FIDIV [mem32int]
FIDIV [mem16int]
FIDIVR [mem32int]
FIDIVR [mem16int]
FILD [mem16int]
FILD [mem32int]
FILD [mem64int]
FIMUL [mem32int]
FIMUL [mem16int]
FINCSTP
FINIT
FIST [mem16int]
FIST [mem32int]
FISTP [mem16int]
FISTP [mem32int]
FISTP [mem64int]
FISUB [mem32int]
FISUB [mem16int]
FISUBR [mem32int]
FISUBR [mem16int]
FLD ST(i)
FLD [mem32real]
FLD [mem64real]
FLD [mem80real]
FLD1
Notes:
1. The last three bits of the modR/M byte select the stack entry ST(i).
214
First Second ModR/M
Byte Byte Byte
DAh mm-000-xxx VectorPath
DEh mm-000-xxx VectorPath
DAh mm-010-xxx VectorPath
DEh mm-010-xxx VectorPath
DAh mm-011-xxx VectorPath
DEh mm-011-xxx VectorPath
DAh mm-110-xxx VectorPath
DEh mm-110-xxx VectorPath
DAh mm-111-xxx VectorPath
DEh mm-111-xxx VectorPath
DFh mm-000-xxx DirectPath
DBh mm-000-xxx DirectPath
DFh mm-101-xxx DirectPath
DAh mm-001-xxx VectorPath
DEh mm-001-xxx VectorPath
D9h F7h
DBh E3h
DFh mm-010-xxx DirectPath
DBh mm-010-xxx DirectPath
DFh mm-011-xxx DirectPath
DBh mm-011-xxx DirectPath
DFh mm-111-xxx DirectPath
DAh mm-100-xxx VectorPath
DEh mm-100-xxx VectorPath
DAh mm-101-xxx VectorPath
DEh mm-101-xxx VectorPath
D9h 11-000-xxx
D9h mm-000-xxx DirectPath FADD/FMUL/FSTORE
DDh mm-000-xxx DirectPath FADD/FMUL/FSTORE
DBh mm-101-xxx VectorPath
D9h E8h
Decode FPU
Type Pipe(s)
FSTORE
FSTORE
FSTORE
DirectPath FADD/FMUL/FSTORE
VectorPath
FSTORE
FSTORE
FSTORE
FSTORE
FSTORE
DirectPath FADD/FMUL
DirectPath FSTORE
Instruction Dispatch and Execution Resources
22007E/0—November 1999
Note
1