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AMD SP5100 Databook
44409 Rev. 1.70 October 10
8.3
LPC ISA Bridge
8.3.1 LPC Interface Overview
The Low Pin Count (LPC) bus interface is a cost-efficient, low-speed interface designed to support low-
speed legacy (ISA, X-bus) devices. The LPC interface essentially eliminates the need of ISA and X-bus in
the system. A typical setup of the system with LPC interface is shown in Figure 8-2 below. Here the ISA
bus is internal to SP5100 and is used for connecting to the legacy DMA logic. The LPC controller
connects to the A-Link bus on one side and the LPC and SPI bus on the other side.
A-Link bus
LPC Host Controller
LPC-SPI
bridge
LPC Device
SPI Device
Figure 8-2: A Typical LPC Bus System
Examples of LPC devices include Super I/O (floppy-disk controller, keyboard controller), BIOS, audio,
TPM, and system management controller. BIOS ROM can also be populated on the SPI interface.
SP5100 can support FWH, LPC, or SPI type BIOS ROM. The ROM selection is determined by two strap
pins during RSMRST# assertion. In addition to the straps, software can change the ROM selection
through programming in the PMIO registers. SP5100 SPI interface is designed to allow ROM sharing
with an external device such as an Ethernet MAC to save BOM cost. (Note: Device that shares the ROM
must follow AMD SPI ROM sharing specification).
Note that the ISA interface is only used for legacy DMA operation. LPC host controller has the A-Link
interface on one side and LPC interface on the other. Some LPC signals are optional. A more detailed
description of each signal is given in
section
7.2.
The host controller supports memory and IO read/write, DMA read/write, and bus master memory/IO
54
Functional Description
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