Load/Store Pipeline Operations; Table 6. Load/Store Unit Stages - AMD Athlon Processor x86 Optimization Manual

22007E/0—November 1999

Load/Store Pipeline Operations

Execution Unit Resources
The AMD Athlon processor decodes any instruction that
references memory into primitive load/store operations. For
example, consider the following code sample:
MOV AX, [EBX]
PUSH EAX
POP EAX
ADD [EAX], EBX
FSTP [EAX]
MOVQ [EAX], MM0
As shown in Table 6, the load/store unit (LSU) consists of a
three-stage data cache lookup.
Table 6. Load/Store Unit Stages
Stage 1 (Cycle 8)
Address Calculation / LS1
Scan
Loads and stores are first dispatched in order into a 12-entry
deep reservation queue called LS1. LS1 holds loads and stores
that are waiting to enter the cache subsystem. Loads and stores
are allocated into LS1 entries at dispatch time in program
order, and are required by LS1 to probe the data cache in
program order. The AGUs can calculate addresses out of
program order, therefore, LS1 acts as an address reorder buffer.
When a load or store is scanned out of the LS1 queue (Stage 1),
it is deallocated from the LS1 queue and inserted into the data
cache probe pipeline (Stage 2 and Stage 3). Up to two memory
operations can be scheduled (scanned out of LS1) to access the
data cache per cycle. The LSU can handle the following:
Two 64-bit loads per cycle or
One 64-bit load and one 64-bit store per cycle or
Two 32-bit stores per cycle
AMD Athlon™ Processor x86 Code Optimization
;1 load MacroOP
;1 store MacroOP
;1 load MacroOP
;1 load/store and 1 IEU MacroOPs
;1 store MacroOP
;1 store MacroOP
Stage 2 (Cycle 9)
Transport Address to Data
Cache
Stage 3 (Cycle 10)
Data Cache Access / LS2
Data Forward
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