AMD Athlon Processor x86 Optimization Manual page 216

AMD Athlon™ Processor x86 Code Optimization
Table 19. Integer Instructions (Continued)
Instruction Mnemonic
POP EBX
POP ESP
POP EBP
POP ESI
POP EDI
POP mreg 16/32
POP mem 16/32
POPA/POPAD
POPF/POPFD
PUSH ES
PUSH CS
PUSH FS
PUSH GS
PUSH SS
PUSH DS
PUSH EAX
PUSH ECX
PUSH EDX
PUSH EBX
PUSH ESP
PUSH EBP
PUSH ESI
PUSH EDI
PUSH imm8
PUSH imm16/32
PUSH mreg16/32
PUSH mem16/32
PUSHA/PUSHAD
PUSHF/PUSHFD
RCL mreg8, imm8
RCL mem8, imm8
RCL mreg16/32, imm8
RCL mem16/32, imm8
200
First Second ModR/M
Byte Byte Byte
5Bh
5Ch
5Dh
5Eh
5Fh
8Fh 11-000-xxx
8Fh mm-000-xxx VectorPath
61h
9Dh
06h
0Eh
0Fh A0h
0Fh A8h
16h
1Eh
50h
51h
52h
53h
54h
55h
56h
57h
6Ah
68h
FFh 11-110-xxx
FFh mm-110-xxx VectorPath
60h
9Ch
C0h 11-010-xxx
C0h mm-010-xxx VectorPath
C1h 11-010-xxx
C1h mm-010-xxx VectorPath
Instruction Dispatch and Execution Resources
22007E/0—November 1999
Decode
Type
VectorPath
VectorPath
VectorPath
VectorPath
VectorPath
VectorPath
VectorPath
VectorPath
VectorPath
VectorPath
VectorPath
VectorPath
VectorPath
VectorPath
DirectPath
DirectPath
DirectPath
DirectPath
DirectPath
DirectPath
DirectPath
DirectPath
DirectPath
DirectPath
VectorPath
VectorPath
VectorPath
DirectPath
DirectPath