Appendix F Instruction Dispatch And Execution Resources - AMD Athlon Processor x86 Optimization Manual

22007E/0—November 1999
Instruction Dispatch and Execution Resources
Instruction Dispatch and
Execution Resources
This chapter describes the MacroOPs generated by each
decoded instruction, along with the relative static execution
latencies of these groups of operations. Tables 19 through 24
starting on page 188 define the integer, MMX™, MMX
extensions, floating-point, 3DNow!™, and 3DNow! extensions
instructions, respectively.
The first column in these tables indicates the instruction
mnemonic and operand types with the following notations:
reg8—byte integer register defined by instruction byte(s) or
bits 5, 4, and 3 of the modR/M byte
mreg8—byte integer register defined by bits 2, 1, and 0 of
the modR/M byte
reg16/32—word and doubleword integer register defined by
instruction byte(s) or bits 5, 4, and 3 of the modR/M byte
mreg16/32—word and doubleword integer register defined
by bits 2, 1, and 0 of the modR/M byte
mem8—byte memory location
mem16/32—word or doubleword memory location
mem32/48—doubleword or 6-byte memory location
mem48—48-bit integer value in memory
mem64—64-bit value in memory
imm8/16/32—8-bit, 16-bit or 32-bit immediate value
disp8—8-bit displacement value
AMD Athlon™ Processor x86 Code Optimization
Appendix F
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