AMD Athlon Processor x86 Optimization Manual page 98

AMD Athlon™ Processor x86 Code Optimization
82
by 11: LEA REG2, [REG1*8+REG1]
ADD REG1, REG1
ADD REG1, REG2
by 12: SHL REG1, 2
LEA REG1, [REG1*2+REG1]
by 13: LEA REG2, [REG1*2+REG1]
SHL REG1, 4
SUB REG1, REG2
by 14: LEA REG2, [REG1*4+REG1]
LEA REG1, [REG1*8+REG1]
ADD REG1, REG2
by 15: MOV REG2, REG1
SHL REG1, 4
SUB REG1, REG2
by 16: SHL REG1, 4
by 17: MOV REG2, REG1
SHL REG1, 4
ADD REG1, REG2
by 18: ADD REG1, REG1
LEA REG1, [REG1*8+REG1]
by 19: LEA REG2, [REG1*2+REG1]
SHL REG1, 4
ADD REG1, REG2
by 20: SHL REG1, 2
LEA REG1, [REG1*4+REG1]
by 21: LEA REG2, [REG1*4+REG1]
SHL REG1, 4
ADD REG1, REG2
by 22: use IMUL
by 23: LEA REG2, [REG1*8+REG1]
SHL REG1, 5
SUB REG1, REG2
by 24: SHL REG1, 3
LEA REG1, [REG1*2+REG1]
by 25: LEA REG2, [REG1*8+REG1]
SHL REG1, 4
ADD REG1, REG2
Use Alternative Code When Multiplying by a Constant
22007E/0—November 1999
;3 cycles
;3 cycles
;3 cycles
;3 cycles
;2 cycles
;1 cycle
;2 cycles
;3 cycles
;3 cycles
;3 cycles
;3 cycles
;3 cycles
;3 cycles
;3 cycles