Figure 13. Mtrr Capability Register Format; Table 12. Memory Type Encodings - AMD Athlon Processor x86 Optimization Manual

AMD Athlon™ Processor x86 Code Optimization
Memory Types

Table 12. Memory Type Encodings

Type Number
00h UC—Uncacheable
01h WC—Write-Combining
04h WT—Writethrough
05h WP—Write-Protect
06h WB—Writeback
MTRR Capability
Register Format
63
Reserved
Symbol Description
WC Write Combining Memory Type 10
FIX Fixed Range Registers
VCNT No. of Variable Range Registers 7–0

Figure 13. MTRR Capability Register Format

174
Five standard memory types are defined by the AMD Athlon
processor: writethrough (WT), writeback (WB), write-protect
(WP), write-combining (WC), and uncacheable (UC). These are
described in Table 12 on page 174.
Type Name
Uncacheable for reads or writes. Cannot be combined. Must be
non-speculative for reads or writes.
Uncacheable for reads or writes. Can be combined. Can be speculative for
reads. Writes can never be speculative.
Reads allocate on a miss, but only to the S-state. Writes do not allocate on
a miss and, for a hit, writes update the cached entry and main memory.
WP is functionally the same as the WT memory type, except stores do not
actually modify cached data and do not cause an exception.
Reads will allocate on a miss, and will allocate to:
S
M state if returned with a ReadDataDirty command.
Writes allocate to the M state, if the read allows the line to be marked E.
The MTRR capability register is a read-only register that
defines the specific MTRR capability of the processor and is
defined as follows.
Bits
8
For the AMD Athlon processor, the MTRR capability register
should contain 0508h (write-combining, fixed MTRR s
supported, and eight variable MTRRs defined).
Type Description
state if returned with a ReadDataShared command.
11 10
W
C
Memory Type Range Register (MTRR) Mechanism
22007E/0—November 1999
9 8 7 0
F
I VCNT
X