AMD Athlon Processor x86 Optimization Manual page 118

AMD Athlon™ Processor x86 Code Optimization
102
Example 3 (Potentially faster):
MOV ECX, DWORD PTR[X+4]
XOR EDX, EDX
MOV EAX, ECX
AND ECX, 07FF00000h
CMP ECX, 03FF00000h
JB $DONE2
MOV EDX, DWORD PTR[X]
SHR ECX, 20
SHRD EDX, EAX, 21
NEG ECX
ADD ECX, 1054
OR EDX, 080000000h
SAR EAX, 31
SHR EDX, CL
XOR EDX, EAX
SUB EDX, EAX
$DONE2:
MOV [I], EDX
For applications which can tolerate a floating-point-to-integer
conversion that is not compliant with existing programming
language standards (but is IEEE-754 compliant), perform the
conversion using the rounding mode that is currently in effect
(usually round-to-nearest-even).
Example 4 (Fastest):
FLD QWORD PTR [X]
FISTP DWORD PTR [I]
Some compilers offer an option to use the code from example 4
for floating-point-to-integer conversion, using the default
rounding mode.
Lastly, consider setting the rounding mode throughout an
application to truncate and using the code from example 4 to
perform extremely fast conversions that are compliant with
language standards and IEEE-754. This mode is also provided
as an option by some compilers. Note that use of this technique
also changes the rounding mode for all other FPU operations
inside the application, which can lead to significant changes in
numerical results and even program failure (for example, due to
lack of convergence in iterative algorithms).
;get upper 32 bits of double
;i = 0
;save sign bit
;isolate exponent field
;if abs(x) < 1.0
; then i = 0
;get lower 32 bits of double
;extract exponent
;extract mantissa
;compute shift factor for extracting
;non-fractional mantissa bits
;set integer bit of mantissa
;x < 0 ? 0xffffffff : 0
;i = trunc(abs(x))
;i = x < 0 ? ~i : i
;i = x < 0 ? -i : i
;store result
; get double to be converted
; store integer result
Minimize Floating-Point-to-Integer Conversions
22007E/0—November 1999