Figure 5. Fetch/Scan/Align/Decode Pipeline Hardware; Figure 6. Fetch/Scan/Align/Decode Pipeline Stages - AMD Athlon Processor x86 Optimization Manual

AMD Athlon™ Processor x86 Code Optimization
V ec to rP ath
V ec to rP ath
1 6 b yte s
I-C A C H E
D ire ctP a th D ire ctP a th
F E T C H S C A N A L IG N 1 /
1
2

Figure 5. Fetch/Scan/Align/Decode Pipeline Hardware

1
F E T C H

Figure 6. Fetch/Scan/Align/Decode Pipeline Stages

142
E n try
P o in t
D ec o d e
M R O M
Q u ad w o rd
Q u eu e
A L IG N 2/
M E C T L M E R O M
3
The most common x86 instructions flow through the DirectPath
pipeline stages and are decoded by hardware. The less common
instructions, which require microcode assistance, flow through
the VectorPath. Although the DirectPath decodes the common
x86 instructions, it also contains VectorPath instruction data,
which allows it to maintain dispatch order at the end of cycle 5.
2
3
D ire ctP a th
A L IG N 1
S C A N
M E C T L
V e cto rP a th
D ec o d e
D ec o d e
D ec o d e
D ec o d e
D ec o d e
D ec o d e
D ec o d e
D ec o d e
D ec o d e
E D E C /
M E D E C
4 5
4
A L IG N 2 E D E C
M E R O M M E S E Q
Fetch and Decode Pipeline Stages
22007E/0—November 1999
3
M a cro O p s
ID E C
6
5
6
ID E C