AMD Athlon Processor x86 Optimization Manual page 225

22007E/0—November 1999
Table 20. MMX™ Instructions (Continued)
Instruction Mnemonic
PANDN mmreg1, mmreg2
PANDN mmreg, mem64
PCMPEQB mmreg1, mmreg2
PCMPEQB mmreg, mem64
PCMPEQD mmreg1, mmreg2
PCMPEQD mmreg, mem64
PCMPEQW mmreg1, mmreg2
PCMPEQW mmreg, mem64
PCMPGTB mmreg1, mmreg2
PCMPGTB mmreg, mem64
PCMPGTD mmreg1, mmreg2
PCMPGTD mmreg, mem64
PCMPGTW mmreg1, mmreg2
PCMPGTW mmreg, mem64
PMADDWD mmreg1, mmreg2
PMADDWD mmreg, mem64
PMULHW mmreg1, mmreg2
PMULHW mmreg, mem64
PMULLW mmreg1, mmreg2
PMULLW mmreg, mem64
POR mmreg1, mmreg2
POR mmreg, mem64
PSLLD mmreg1, mmreg2
PSLLD mmreg, mem64
PSLLD mmreg, imm8
PSLLQ mmreg1, mmreg2
PSLLQ mmreg, mem64
PSLLQ mmreg, imm8
PSLLW mmreg1, mmreg2
PSLLW mmreg, mem64
PSLLW mmreg, imm8
Notes:
1. Bits 2, 1, and 0 of the modR/M byte select the integer register.
Instruction Dispatch and Execution Resources
Prefix First ModR/M
Byte(s) Byte Byte
0Fh DFh 11-xxx-xxx
0Fh DFh mm-xxx-xxx DirectPath
0Fh 74h 11-xxx-xxx
0Fh 74h mm-xxx-xxx DirectPath
0Fh 76h 11-xxx-xxx
0Fh 76h mm-xxx-xxx DirectPath
0Fh 75h 11-xxx-xxx
0Fh 75h mm-xxx-xxx DirectPath
0Fh 64h 11-xxx-xxx
0Fh 64h mm-xxx-xxx DirectPath
0Fh 66h 11-xxx-xxx
0Fh 66h mm-xxx-xxx DirectPath
0Fh 65h 11-xxx-xxx
0Fh 65h mm-xxx-xxx DirectPath
0Fh F5h 11-xxx-xxx
0Fh F5h mm-xxx-xxx DirectPath
0Fh E5h 11-xxx-xxx
0Fh E5h mm-xxx-xxx DirectPath
0Fh D5h 11-xxx-xxx
0Fh D5h mm-xxx-xxx DirectPath
0Fh EBh 11-xxx-xxx
0Fh EBh mm-xxx-xxx DirectPath
0Fh F2h 11-xxx-xxx
0Fh F2h mm-xxx-xxx DirectPath
0Fh 72h 11-110-xxx
0Fh F3h 11-xxx-xxx
0Fh F3h mm-xxx-xxx DirectPath
0Fh 73h 11-110-xxx
0Fh F1h 11-xxx-xxx
0Fh F1h mm-xxx-xxx DirectPath
0Fh 71h 11-110-xxx
AMD Athlon™ Processor x86 Code Optimization
Decode
FPU Pipe(s)
Type
DirectPath FADD/FMUL
FADD/FMUL
DirectPath FADD/FMUL
FADD/FMUL
DirectPath FADD/FMUL
FADD/FMUL
DirectPath FADD/FMUL
FADD/FMUL
DirectPath FADD/FMUL
FADD/FMUL
DirectPath FADD/FMUL
FADD/FMUL
DirectPath FADD/FMUL
FADD/FMUL
DirectPath FMUL
FMUL
DirectPath FMUL
FMUL
DirectPath FMUL
FMUL
DirectPath FADD/FMUL
FADD/FMUL
DirectPath FADD/FMUL
FADD/FMUL
DirectPath FADD/FMUL
DirectPath FADD/FMUL
FADD/FMUL
DirectPath FADD/FMUL
DirectPath FADD/FMUL
FADD/FMUL
DirectPath FADD/FMUL
Notes
209